A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based ad...
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| Vydáno v: | IEEE transactions on circuits and systems for video technology Ročník 22; číslo 11; s. 1604 - 1610 |
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| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York, NY
IEEE
01.11.2012
Institute of Electrical and Electronics Engineers |
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| ISSN: | 1051-8215, 1558-2205 |
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| Abstract | To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology. |
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| AbstractList | To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology. |
| Author | Gwo-Long Li Yuan-Hsin Liao Tian-Sheuan Chang |
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| Keywords | Video coding High resolution VLSI circuit H.264 Information rate Context-adaptive variable length decoder (CAVLD) Decoding circuit Entropy Information transmission Adaptive decoding Implementation Video signal processing Adaptive coding Time resolution Performance requirement Complementary MOS technology Integrated circuit Critical path Delay time Variable length code Comparative study |
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| SubjectTerms | Applied sciences Circuit properties Coding, codes Context-adaptive variable length decoder (CAVLD) Decoding Delay Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoding Exact sciences and technology H.264 Image processing Information, signal and communications theory Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Signal convertors Signal processing Telecommunications and information theory Throughput Video coding |
| Title | A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video |
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