High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm

Providing superior algorithm-level performance, the non-binary low-density parity-check (NB-LDPC) code is now expected to be one of the next-generation error-correction codes. However, it is hard to implement a high-throughput NB-LDPC decoder in practice due to its impractical processing complexity...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits Vol. 57; no. 10; pp. 2969 - 2978
Main Authors: Choe, Jeongwon, Lee, Youngjoo
Format: Journal Article
Language:English
Published: New York IEEE 01.10.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Codes
Complexity theory
Decoding
Energy management
Error correcting codes
Error correction
Error-correction codes
high-throughput extended min-sum (EMS) decoder
Iterative decoding
non-binary low-density parity-check (NB-LDPC) codes
Optimization
Parallel processing
Performance degradation
Reliability
sorter optimization
Throughput
VLSI design
ISSN:0018-9200, 1558-173X
Online Access:Get full text
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Summary:Providing superior algorithm-level performance, the non-binary low-density parity-check (NB-LDPC) code is now expected to be one of the next-generation error-correction codes. However, it is hard to implement a high-throughput NB-LDPC decoder in practice due to its impractical processing complexity and the excessively long decoding time. Based on the previous extended min-sum (EMS) approach, in this work, we introduce the parallel EMS (pEMS) decoding algorithm that reduces the processing latency of each iteration by managing multiple message entries at a time. The previous two-phase node-level operation is modified to promote the proposed parallel processing without performance degradation, where the delay overheads are minimized by carefully optimizing the internal sorters with input attributes. In addition, the data accessing sequence is precisely adjusted to reduce the number of waiting cycles, further increasing the overall processing efficiency. Implemented in a 22-nm FinFET technology, as a result, the prototype two-parallel decoder for (160, 80) NB-LDPC codes operates at the speed of 950 MHz, achieving the decoding throughput of more than 7 Gb/s, which is 3.2 times faster than the state-of-the-art design.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2022.3176347