A systolic architecture for modulo multiplication

With the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A /spl theta/(log n) algorithm for large moduli multiplication for RNS based architectu...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Jg. 42; H. 11; S. 725 - 729
Hauptverfasser: Elleithy, K.M., Bayoumi, M.A.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York, NY IEEE 01.11.1995
Institute of Electrical and Electronics Engineers
Schlagworte:
ISSN:1057-7130
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:With the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A /spl theta/(log n) algorithm for large moduli multiplication for RNS based architectures. A systolic array has been designed to perform the modulo multiplication algorithm. The proposed modulo multiplier is much faster than previously proposed multipliers and more area efficient. The implementation of this multiplier is modular and is based on using simple cells which leads to efficient VLSI realization. A VLSI implementation using 3 micron CMOS technology shows that a pipelined n-bit module multiplication scheme can operate with a throughput of 30 M operation per second.< >
Bibliographie:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1057-7130
DOI:10.1109/82.475251