A systolic architecture for modulo multiplication

With the current advances in VLSI technology, traditional algorithms for Residue Number System (RNS) based architectures should be reevaluated to explore the new technology dimensions. In this brief, we introduce A /spl theta/(log n) algorithm for large moduli multiplication for RNS based architectu...

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Vydáno v:	IEEE transactions on circuits and systems. 2, Analog and digital signal processing Ročník 42; číslo 11; s. 725 - 729
Hlavní autoři:	Elleithy, K.M., Bayoumi, M.A.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York, NY IEEE 01.11.1995 Institute of Electrical and Electronics Engineers
Témata:	Acceleration Adders Algorithm design and analysis Applied sciences CMOS technology Digital arithmetic Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Minerals Petroleum Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Systolic arrays Throughput Very large scale integration Arithmetic circuit VLSI circuit Circuit design Complementary MOS technology Multiplier Adder Systolic network Implementation
ISSN:	1057-7130
On-line přístup:	Získat plný text
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