Elleithy, K., & Bayoumi, M. (1995). A systolic architecture for modulo multiplication. IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 42(11), 725-729. https://doi.org/10.1109/82.475251
Citace podle Chicago (17th ed.)Elleithy, K.M, a M.A Bayoumi. "A Systolic Architecture for Modulo Multiplication." IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing 42, no. 11 (1995): 725-729. https://doi.org/10.1109/82.475251.
Citace podle MLA (9th ed.)Elleithy, K.M, a M.A Bayoumi. "A Systolic Architecture for Modulo Multiplication." IEEE Transactions on Circuits and Systems. 2, Analog and Digital Signal Processing, vol. 42, no. 11, 1995, pp. 725-729, https://doi.org/10.1109/82.475251.
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