Toward Efficient FPGA Accelerator DSE via Hierarchical and RM-Guided Methods - Shi, Chao; Cheng, Qianyu; Wang, Teng; Wang, Chao; Zhou, Xuehai (IEEE embedded systems letters, 2025)
field-programmable gate array (FPGA) accelerator design has gradually become a mainstream acceleration solution, widely applied in fields, such as large language models, deep learning inference, autonomous driving, real-time 3-D scene reconstruction, and embedded intelligent terminals. high-level synthesis (HLS) technology has provided significant support for FPGA accelerator design, greatly improving design efficiency and flexibility. However, manual parameter tuning by designers is still required to achieve optimal performance. Existing research has proposed automated design space exploration (DSE) methods to assist in parameter tuning, but these methods often exhibit low efficiency when dealing with complex HLS designs and, in some cases, fail to function properly. To address this, we present an efficient DSE method guided by hierarchical analysis and rule mining (RM), aimed at tackling more complex design challenges. This approach performs hierarchical analysis of design solutions and integrates RM techniques to optimize the design space search process, enabling efficient exploration of superior design solutions. Experimental results show that our method achieves performance comparable to state-of-the-art (SOTA) techniques, while delivering a speed-up of 3.6{× } to 30.4{× } . Moreover, it enables the effective exploration of complex design spaces that existing methods struggle to handle.