A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

Advances in static random access memory (SRAM)-CIM devices are meant to increase capacity while improving energy efficiency (EF) and reducing computing latency (<inline-formula> <tex-math notation="LaTeX">T_{\mathrm {AC}} </tex-math></inline-formula>). This work pre...

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Veröffentlicht in:	IEEE journal of solid-state circuits Jg. 58; H. 3; S. 877 - 892
Hauptverfasser:	Su, Jian-Wei, Chou, Yen-Chi, Liu, Ruhui, Liu, Ta-Wei, Lu, Pei-Jung, Wu, Ping-Chun, Chung, Yen-Lin, Hong, Li-Yang, Ren, Jin-Sheng, Pan, Tianlong, Jhang, Chuan-Jia, Huang, Wei-Hsing, Chien, Chih-Han, Mei, Peng-I, Li, Sih-Han, Sheu, Shyh-Shyuan, Chang, Shih-Chieh, Lo, Wei-Chung, Wu, Chih-I, Si, Xin, Lo, Chung-Chuan, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Chang, Meng-Fan
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.03.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Analog to digital converters Artificial intelligence Artificial intelligence (AI) Capacitance charge sharing Common Information Model (computing) Common Information Model (electricity) Computation computing-in-memory (CIM) Energy consumption inference Logic gates Memory devices Multiplication Random access memory Signal processing SRAM cells Static random access memory static random access memory (SRAM) Transistors
ISSN:	0018-9200, 1558-173X
Online-Zugang:	Volltext
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