A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

Advances in static random access memory (SRAM)-CIM devices are meant to increase capacity while improving energy efficiency (EF) and reducing computing latency (<inline-formula> <tex-math notation="LaTeX">T_{\mathrm {AC}} </tex-math></inline-formula>). This work pre...

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Published in:	IEEE journal of solid-state circuits Vol. 58; no. 3; pp. 877 - 892
Main Authors:	Su, Jian-Wei, Chou, Yen-Chi, Liu, Ruhui, Liu, Ta-Wei, Lu, Pei-Jung, Wu, Ping-Chun, Chung, Yen-Lin, Hong, Li-Yang, Ren, Jin-Sheng, Pan, Tianlong, Jhang, Chuan-Jia, Huang, Wei-Hsing, Chien, Chih-Han, Mei, Peng-I, Li, Sih-Han, Sheu, Shyh-Shyuan, Chang, Shih-Chieh, Lo, Wei-Chung, Wu, Chih-I, Si, Xin, Lo, Chung-Chuan, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Chang, Meng-Fan
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Analog to digital converters Artificial intelligence Artificial intelligence (AI) Capacitance charge sharing Common Information Model (computing) Common Information Model (electricity) Computation computing-in-memory (CIM) Energy consumption inference Logic gates Memory devices Multiplication Random access memory Signal processing SRAM cells Static random access memory static random access memory (SRAM) Transistors
ISSN:	0018-9200, 1558-173X
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Abstract	Advances in static random access memory (SRAM)-CIM devices are meant to increase capacity while improving energy efficiency (EF) and reducing computing latency (<inline-formula> <tex-math notation="LaTeX">T_{\mathrm {AC}} </tex-math></inline-formula>). This work presents a novel SRAM-CIM structure using: 1) a segmented-bitline charge-sharing (SBCS) scheme for multiply-and-accumulate (MAC) operations with low energy consumption and a consistently high signal margin across MAC values; 2) a bitline-combining (BL-CMB) scheme to reduce the number of analog-to-digital converters (ADCs) and, thereby, provide options in determining a tradeoff between EF and inference accuracy; 3) a source-injection local-multiplication cell (SILMC) connected to two types of global-bitline-switch to support the SBCS and BL-CMB schemes with consistent signal margin against process variation in transistors; and 4) prioritized-hybrid ADC to suppress area and power overhead for analog readout operations. We fabricated a 28-nm 384-kb SRAM-CIM macro using foundry-provided compact-6T cells supporting MAC operations with 16 accumulations of 8-b input and 8-b weight with near-full precision output (20 b). This macro achieved <inline-formula> <tex-math notation="LaTeX">T_{\mathrm {AC}} </tex-math></inline-formula> of 7.2 ns and EF of 22.75 TOPS/W performing 8-b-MAC operations.
AbstractList	Advances in static random access memory (SRAM)-CIM devices are meant to increase capacity while improving energy efficiency (EF) and reducing computing latency (<inline-formula> <tex-math notation="LaTeX">T_{\mathrm {AC}} </tex-math></inline-formula>). This work presents a novel SRAM-CIM structure using: 1) a segmented-bitline charge-sharing (SBCS) scheme for multiply-and-accumulate (MAC) operations with low energy consumption and a consistently high signal margin across MAC values; 2) a bitline-combining (BL-CMB) scheme to reduce the number of analog-to-digital converters (ADCs) and, thereby, provide options in determining a tradeoff between EF and inference accuracy; 3) a source-injection local-multiplication cell (SILMC) connected to two types of global-bitline-switch to support the SBCS and BL-CMB schemes with consistent signal margin against process variation in transistors; and 4) prioritized-hybrid ADC to suppress area and power overhead for analog readout operations. We fabricated a 28-nm 384-kb SRAM-CIM macro using foundry-provided compact-6T cells supporting MAC operations with 16 accumulations of 8-b input and 8-b weight with near-full precision output (20 b). This macro achieved <inline-formula> <tex-math notation="LaTeX">T_{\mathrm {AC}} </tex-math></inline-formula> of 7.2 ns and EF of 22.75 TOPS/W performing 8-b-MAC operations. Advances in static random access memory (SRAM)-CIM devices are meant to increase capacity while improving energy efficiency (EF) and reducing computing latency ([Formula Omitted]). This work presents a novel SRAM-CIM structure using: 1) a segmented-bitline charge-sharing (SBCS) scheme for multiply-and-accumulate (MAC) operations with low energy consumption and a consistently high signal margin across MAC values; 2) a bitline-combining (BL-CMB) scheme to reduce the number of analog-to-digital converters (ADCs) and, thereby, provide options in determining a tradeoff between EF and inference accuracy; 3) a source-injection local-multiplication cell (SILMC) connected to two types of global-bitline-switch to support the SBCS and BL-CMB schemes with consistent signal margin against process variation in transistors; and 4) prioritized-hybrid ADC to suppress area and power overhead for analog readout operations. We fabricated a 28-nm 384-kb SRAM-CIM macro using foundry-provided compact-6T cells supporting MAC operations with 16 accumulations of 8-b input and 8-b weight with near-full precision output (20 b). This macro achieved [Formula Omitted] of 7.2 ns and EF of 22.75 TOPS/W performing 8-b-MAC operations.
Author	Jhang, Chuan-Jia Su, Jian-Wei Lo, Chung-Chuan Liu, Ren-Shuo Chien, Chih-Han Tang, Kea-Tiong Lu, Pei-Jung Chou, Yen-Chi Lo, Wei-Chung Si, Xin Pan, Tianlong Wu, Chih-I Li, Sih-Han Liu, Ta-Wei Chung, Yen-Lin Huang, Wei-Hsing Sheu, Shyh-Shyuan Ren, Jin-Sheng Hong, Li-Yang Chang, Meng-Fan Mei, Peng-I Wu, Ping-Chun Hsieh, Chih-Cheng Liu, Ruhui Chang, Shih-Chieh
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SubjectTerms	Analog to digital converters Artificial intelligence Artificial intelligence (AI) Capacitance charge sharing Common Information Model (computing) Common Information Model (electricity) Computation computing-in-memory (CIM) Energy consumption inference Logic gates Memory devices Multiplication Random access memory Signal processing SRAM cells Static random access memory static random access memory (SRAM) Transistors
Title	A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips
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