Low complexity bit-parallel systolic architecture for computing C+ AB2 over a class of GF(2 m)

This work presents a ringed bit-parallel systolic architecture for computing C+ AB 2 over a class of GF(2 m ) based on the irreducible all one polynomial or the irreducible equally spaced polynomial of degree m, where A, B and C are elements in GF(2 m ). The ringed bit-parallel systolic multiplier o...

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Vydáno v:	Integration (Amsterdam) Ročník 37; číslo 3; s. 167 - 176
Hlavní autoři:	Ting, Yeun-Renn, Lu, Erl-Huei, Lee, Jau-Yien
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Amsterdam Elsevier B.V 01.08.2004 Elsevier Science
Témata:	Applied sciences C+ AB2 Circuit properties Cryptography Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Error control coding Exact sciences and technology Finite field Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Systolic multiplier Systolic multiplier C+ AB 2 Finite field Cryptography Error control coding Arithmetic circuit VLSI circuit Parallel architectures Systolic network Three dimensional model C + AB2 Integrated circuit Multiplier Error correcting code
ISSN:	0167-9260, 1872-7522
On-line přístup:	Získat plný text
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