Low complexity bit-parallel systolic architecture for computing C+ AB2 over a class of GF(2 m)

This work presents a ringed bit-parallel systolic architecture for computing C+ AB 2 over a class of GF(2 m ) based on the irreducible all one polynomial or the irreducible equally spaced polynomial of degree m, where A, B and C are elements in GF(2 m ). The ringed bit-parallel systolic multiplier o...

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Bibliographic Details
Published in:Integration (Amsterdam) Vol. 37; no. 3; pp. 167 - 176
Main Authors: Ting, Yeun-Renn, Lu, Erl-Huei, Lee, Jau-Yien
Format: Journal Article
Language:English
Published: Amsterdam Elsevier B.V 01.08.2004
Elsevier Science
Subjects:
Applied sciences
C+ AB2
Circuit properties
Cryptography
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Error control coding
Exact sciences and technology
Finite field
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Systolic multiplier
Systolic multiplier
C+ AB 2
Finite field
Cryptography
Error control coding
Arithmetic circuit
VLSI circuit
Parallel architectures
Systolic network
Three dimensional model
C + AB2
Integrated circuit
Multiplier
Error correcting code
ISSN:0167-9260, 1872-7522
Online Access:Get full text
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Summary:This work presents a ringed bit-parallel systolic architecture for computing C+ AB 2 over a class of GF(2 m ) based on the irreducible all one polynomial or the irreducible equally spaced polynomial of degree m, where A, B and C are elements in GF(2 m ). The ringed bit-parallel systolic multiplier over the class of GF(2 m ) is free of global connections and requires fewer gates and input pins than the other relative multipliers proposed in Liu et al. (IEICE Trans. Fundam. E83-A (12) (2000) 2657) and Lee et al. (IEEE Trans. Circuits Syst. II 48(5) (2001) 519; 15th IEEE Symposium on Computer Arithmetic (Arith-2001), Vail, CO, USA, June 2001, p. 51). Moreover, this ringed configuration can be easily implemented in VLSI systems by taking the advantage of three-dimensional routing.
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ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2004.01.003