APA (7th ed.) Citation

Ting, Y., Lu, E., & Lee, J. (2004). Low complexity bit-parallel systolic architecture for computing C+ AB2 over a class of GF(2 m). Integration (Amsterdam), 37(3), 167-176. https://doi.org/10.1016/j.vlsi.2004.01.003

Chicago Style (17th ed.) Citation

Ting, Yeun-Renn, Erl-Huei Lu, and Jau-Yien Lee. "Low Complexity Bit-parallel Systolic Architecture for Computing C+ AB2 over a Class of GF(2 M)." Integration (Amsterdam) 37, no. 3 (2004): 167-176. https://doi.org/10.1016/j.vlsi.2004.01.003.

MLA (9th ed.) Citation

Ting, Yeun-Renn, et al. "Low Complexity Bit-parallel Systolic Architecture for Computing C+ AB2 over a Class of GF(2 M)." Integration (Amsterdam), vol. 37, no. 3, 2004, pp. 167-176, https://doi.org/10.1016/j.vlsi.2004.01.003.