Thread and Data Mapping in Software Transactional Memory: an Overview
In current microarchitectures, due to the complex memory hierarchies and different latencies on memory accesses, thread and data mapping are important issues to improve application performance. Software transactional memory (STM) is an abstraction used for thread synchronization, replacing the use o...
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| Vydáno v: | International journal of parallel programming Ročník 53; číslo 3; s. 19 |
|---|---|
| Hlavní autoři: | , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York
Springer US
01.06.2025
Springer Nature B.V |
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| ISSN: | 0885-7458, 1573-7640 |
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| Abstract | In current microarchitectures, due to the complex memory hierarchies and different latencies on memory accesses, thread and data mapping are important issues to improve application performance. Software transactional memory (STM) is an abstraction used for thread synchronization, replacing the use of locks in parallel programming. Regarding thread and data mapping, STM presents new challenges and mapping opportunities, since (1) STM can use different conflict detection and resolution strategies, making the behavior of the application less predictable, and; (2) the STM runtime has precise information about shared data and the intensity with each thread accesses them. These unique characteristics provide many opportunities for low-overhead, but precise statistics to guide mapping strategies for STM applications. The main objective of this paper is to survey the existing work about thread and data mapping that uses solely information gathered from the STM runtime to guide thread and data mapping decisions. We also discuss future research directions within this research area. |
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| AbstractList | In current microarchitectures, due to the complex memory hierarchies and different latencies on memory accesses, thread and data mapping are important issues to improve application performance. Software transactional memory (STM) is an abstraction used for thread synchronization, replacing the use of locks in parallel programming. Regarding thread and data mapping, STM presents new challenges and mapping opportunities, since (1) STM can use different conflict detection and resolution strategies, making the behavior of the application less predictable, and; (2) the STM runtime has precise information about shared data and the intensity with each thread accesses them. These unique characteristics provide many opportunities for low-overhead, but precise statistics to guide mapping strategies for STM applications. The main objective of this paper is to survey the existing work about thread and data mapping that uses solely information gathered from the STM runtime to guide thread and data mapping decisions. We also discuss future research directions within this research area. |
| ArticleNumber | 19 |
| Author | Diener, Matthias Du Bois, André Rauber Pasqualin, Douglas Pereira Pilla, Maurício Lima |
| Author_xml | – sequence: 1 givenname: Douglas Pereira orcidid: 0000-0001-6125-8994 surname: Pasqualin fullname: Pasqualin, Douglas Pereira email: dp.pasqualin@inf.ufpel.edu.br organization: Computer Science Graduate Program (PPGC), Universidade Federal de Pelotas – sequence: 2 givenname: Matthias orcidid: 0000-0002-9064-7806 surname: Diener fullname: Diener, Matthias organization: University of Illinois Urbana-Champaign – sequence: 3 givenname: André Rauber orcidid: 0000-0002-6790-5184 surname: Du Bois fullname: Du Bois, André Rauber organization: Computer Science Graduate Program (PPGC), Universidade Federal de Pelotas – sequence: 4 givenname: Maurício Lima orcidid: 0000-0003-2382-2755 surname: Pilla fullname: Pilla, Maurício Lima organization: Computer Science Graduate Program (PPGC), Universidade Federal de Pelotas |
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| SubjectTerms | Computer Science Concurrent processing Hierarchies Mapping Parallel programming Processor Architectures Run time (computers) Software Software Engineering/Programming and Operating Systems Synchronism Theory of Computation |
| Title | Thread and Data Mapping in Software Transactional Memory: an Overview |
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