LHTAM: Low-power and high-speed approximate multiplier for tiny inexact computing systems

The numerical computations related to certain applications can usually withstand a small amount of error. So in these types of applications, such as data mining, encoding algorithms, image processing, machine learning, signal processing, and other error-resilient applications, accurate computing can...

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Bibliographic Details
Published in:Computers & electrical engineering Vol. 123; p. 110215
Main Authors: Izadi, Azin, Jamshidi, Vahid
Format: Journal Article
Language:English
Published: Elsevier Ltd 01.04.2025
Subjects:
Approximate computing
Approximate multiplier
Area
Delay
Energy-consumption
Mitchell’s multiplication algorithm
Energy-consumption
Area
Mitchell’s multiplication algorithm
Approximate computing
Delay
Approximate multiplier
ISSN:0045-7906
Online Access:Get full text
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Summary:The numerical computations related to certain applications can usually withstand a small amount of error. So in these types of applications, such as data mining, encoding algorithms, image processing, machine learning, signal processing, and other error-resilient applications, accurate computing can be replaced with approximate computing in order to reduce circuit delay and power consumption. In these applications, a certain degree of error is acceptable. Multiplication is a fundamental arithmetic operation in computer systems. However, performing it accurately using multipliers — key components in these systems — can result in increased circuit delay, higher power consumption, and greater use of area. Therefore, presenting an optimal multiplier would be considered as a significant advantage for inexact computing systems. In this paper, we propose a new Mitchell algorithm-based approximate multiplier that applied error-reduction factors can be used. The proposed design has been implemented in the Cadence software environment by using TSMC 45 nm standard-cell library and a supplied voltage of 1.1v. The simulation results indicate an average reduction of 31.7% in area, 64.7% in energy, and 36.1% in circuit delay relative to those achieved in previous works. The mean relative error distance (MRED) of the proposed method is 2.6%.
ISSN:0045-7906
DOI:10.1016/j.compeleceng.2025.110215