Synthesis of multilevel NAND gate circuits for incompletely specified multi-output Boolean functions and CAD using permissible cubes and PCRM graphs
A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented. A powerful technique using logic zero-one-interaction of permissible cubes is among the salient features in the synthesizing algorith...
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| Published in: | International journal of electronics Vol. 78; no. 2; pp. 303 - 316 |
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| Main Authors: | , |
| Format: | Journal Article |
| Language: | English |
| Published: |
London
Taylor & Francis Group
01.02.1995
Taylor & Francis |
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| ISSN: | 0020-7217, 1362-3060 |
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| Abstract | A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented. A powerful technique using logic zero-one-interaction of permissible cubes is among the salient features in the synthesizing algorithm developed. Only uncomplemented inputs are involved in this design technique, so fewer NAND gates are required in the synthesized logic network. The algorithm developed is feasible for any number of input variables and any incompletely specified functions. The algorithm is implemented in the C language using a software approach based on our powerful data structure that have also been developed. Permissible-cube-related-minterm (PCRM) graphs generate the set of required permissible cubes automatically. The automatic level-reduction and gate-reduction of logic networks using a CAD approach is also described. The CAD algorithms provide automatic synthesis of nearly minimal multilevel multi-output NAND gate logic networks. |
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| AbstractList | A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented. A powerful technique using logic zero-one-interaction of permissible cubes is among the salient features in the synthesizing algorithm developed. Only uncomplemented inputs are involved in this design technique, so fewer NAND gates are required in the synthesized logic network. The algorithm developed is feasible for any number of input variables and any incompletely specified functions. The algorithm is implemented in the C language using a software approach based on our powerful data structure that have also been developed. Permissible-cube-related-minterm (PCRM) graphs generate the set of required permissible cubes automatically. The automatic level-reduction and gate-reduction of logic networks using a CAD approach is also described. The CAD algorithms provide automatic synthesis of nearly minimal multilevel multi-output NAND gate logic networks. |
| Author | TWU, HORNG-TAY CHEN, LIANG-CHIA |
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| Cites_doi | 10.1147/rd.185.0443 10.1109/TC.1987.1676907 10.1007/978-1-4613-2821-6 10.1109/TCAD.1987.1270347 10.1109/TC.1968.226866 10.1109/43.127616 10.1109/T-C.1969.222593 10.1109/43.67783 10.1109/12.35836 10.1109/TCAD.1986.1270191 |
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| Copyright | Copyright Taylor & Francis Group, LLC 1995 1995 INIST-CNRS |
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| SubjectTerms | Applied sciences Circuit properties Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology |
| Title | Synthesis of multilevel NAND gate circuits for incompletely specified multi-output Boolean functions and CAD using permissible cubes and PCRM graphs |
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