A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance

Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target o...

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Veröffentlicht in:SN computer science Jg. 4; H. 1; S. 77
Hauptverfasser: Selvam, Ravikumar, Tyagi, Akhilesh
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Singapore Springer Nature Singapore 01.01.2023
Springer Nature B.V
Schlagworte:
Algorithms
Capacitance
Circuit design
Computer Imaging
Computer Science
Computer Systems Organization and Communication Networks
Data integrity
Data Structures and Information Theory
Decoupling
Design
Discriminant analysis
Electric power distribution
Information Systems and Communication Service
Integrated circuits
Machine learning
Original Research
Pattern Recognition and Graphics
Propagation
Smart and Connected Electronic Systems
Software Engineering/Programming and Operating Systems
Topology
Vision
Power distribution network
Decoupling capacitance
Side-channel attack
ISSN:2661-8907, 2662-995X, 2661-8907
Online-Zugang:Volltext
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Zusammenfassung:Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current ( I ) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
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content type line 14
ISSN:2661-8907
2662-995X
2661-8907
DOI:10.1007/s42979-022-01491-5