A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance - Selvam, Ravikumar; Tyagi, Akhilesh (SN computer science, 2023)
Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current ( I ) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance.