A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance

Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target o...

Celý popis

Uloženo v:

Podrobná bibliografie
Vydáno v:	SN computer science Ročník 4; číslo 1; s. 77
Hlavní autoři:	Selvam, Ravikumar, Tyagi, Akhilesh
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Singapore Springer Nature Singapore 01.01.2023 Springer Nature B.V
Témata:	Algorithms Capacitance Circuit design Computer Imaging Computer Science Computer Systems Organization and Communication Networks Data integrity Data Structures and Information Theory Decoupling Design Discriminant analysis Electric power distribution Information Systems and Communication Service Integrated circuits Machine learning Original Research Pattern Recognition and Graphics Propagation Smart and Connected Electronic Systems Software Engineering/Programming and Operating Systems Topology Vision Power distribution network Decoupling capacitance Side-channel attack
ISSN:	2661-8907, 2662-995X, 2661-8907
On-line přístup:	Získat plný text
Tagy:	Přidat tag Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!

Abstract	Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current ( I ) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance.
AbstractList	Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current (I) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance. Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current ( I ) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance.
ArticleNumber	77
Author	Tyagi, Akhilesh Selvam, Ravikumar
Author_xml	– sequence: 1 givenname: Ravikumar orcidid: 0000-0001-9950-2251 surname: Selvam fullname: Selvam, Ravikumar email: rkselvam@iastate.edu organization: Department of Electrical and Computer Engineering, Iowa State University – sequence: 2 givenname: Akhilesh surname: Tyagi fullname: Tyagi, Akhilesh organization: Department of Electrical and Computer Engineering, Iowa State University
BookMark	eNp9kMtOwzAQRS1UJErpD7CyxNrgR5zEy6otD6miCx4SK8t1Jq1LcYKdUPH3hAYJVqxmpDn3jnRO0cBXHhA6Z_SSUZpdxYSrTBHKOaEsUYzIIzTkacpIrmg2-LOfoHGMW0oplzRJUjlELxP84Aog043xHnZ4_mF2rWlc5XFV4qUnduNq_FwUeOZiE9yqPdzuodlX4RXvXbPBM7BVW--cX-OpqY11jfEWztBxaXYRxj9zhJ6u54_TW7JY3txNJwtiWS4lKWRGbQIGeJEmqjBC5EyK0gLNbK5ySLnN8xxomYIQXDJpUlpmVPFCrjgIECN00ffWoXpvITZ6W7XBdy81V5wJzqVKO4r3lA1VjAFKXQf3ZsKnZlR_W9S9Rd1Z1AeLWnYh0YdiB_s1hN_qf1JfdRB1nA
Cites_doi	10.1007/3-540-68697-5_9 10.1109/TVLSI.2002.800533 10.1109/VLSID.2018.52 10.1109/TCSI.2018.2872567 10.1007/978-3-642-15031-9_9 10.1007/978-3-540-45146-4_27 10.1109/ICEMIC.2003.237781 10.1007/11894063_19 10.1109/iSES52644.2021.00051 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559151 10.1109/MWSCAS.2000.951474 10.1109/TETC.2014.2303934 10.1109/CJECE.2019.2949934 10.1007/978-3-642-04138-9_12 10.1007/3-540-36400-5_3 10.1007/11935308_38 10.1109/TEMC.2022.3155471 10.1109/MWSCAS.2014.6908367 10.1145/871506.871517 10.1145/3225209.3225212
ContentType	Journal Article
Copyright	The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd 2022. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
Copyright_xml	– notice: The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd 2022. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
DBID	AAYXX CITATION 8FE 8FG AFKRA ARAPS AZQEC BENPR BGLVJ CCPQU DWQXO GNUQQ HCIFZ JQ2 K7- P5Z P62 PHGZM PHGZT PKEHL PQEST PQGLB PQQKQ PQUKI
DOI	10.1007/s42979-022-01491-5
DatabaseName	CrossRef ProQuest SciTech Collection ProQuest Technology Collection ProQuest Central UK/Ireland Advanced Technologies & Computer Science Collection ProQuest Central Essentials ProQuest Central Technology collection ProQuest One Community College ProQuest Central ProQuest Central Student SciTech Premium Collection ProQuest Computer Science Collection Computer Science Database Advanced Technologies & Aerospace Database ProQuest Advanced Technologies & Aerospace Collection ProQuest Central Premium ProQuest One Academic ProQuest One Academic Middle East (New) ProQuest One Academic Eastern Edition (DO NOT USE) ProQuest One Applied & Life Sciences ProQuest One Academic (retired) ProQuest One Academic UKI Edition
DatabaseTitle	CrossRef Advanced Technologies & Aerospace Collection Computer Science Database ProQuest Central Student Technology Collection ProQuest One Academic Middle East (New) ProQuest Advanced Technologies & Aerospace Collection ProQuest Central Essentials ProQuest Computer Science Collection ProQuest One Academic Eastern Edition SciTech Premium Collection ProQuest One Community College ProQuest Technology Collection ProQuest SciTech Collection ProQuest Central Advanced Technologies & Aerospace Database ProQuest One Applied & Life Sciences ProQuest One Academic UKI Edition ProQuest Central Korea ProQuest Central (New) ProQuest One Academic ProQuest One Academic (New)
DatabaseTitleList	Advanced Technologies & Aerospace Collection
Database_xml	– sequence: 1 dbid: P5Z name: Advanced Technologies & Aerospace Database url: https://search.proquest.com/hightechjournals sourceTypes: Aggregation Database
DeliveryMethod	fulltext_linktorsrc
Discipline	Computer Science
EISSN	2661-8907
ExternalDocumentID	10_1007_s42979_022_01491_5
GroupedDBID	0R~ 406 AACDK AAHNG AAJBT AASML AATNV AAUYE ABAKF ABECU ABHQN ABJNI ABMQK ABTEG ABTKH ABWNU ACAOD ACDTI ACHSB ACOKC ACPIV ACZOJ ADKNI ADTPH ADYFF AEFQL AEMSY AESKC AFBBN AFKRA AFQWF AGMZJ AGQEE AGRTI AIGIU AILAN AJZVZ ALMA_UNASSIGNED_HOLDINGS AMXSW AMYLF ARAPS BAPOH BENPR BGLVJ CCPQU DPUIP EBLON EBS FIGPU FNLPD GGCAI GNWQR HCIFZ IKXTQ IWAJR JZLTJ K7- LLZTM NPVJJ NQJWS OK1 PT4 ROL RSV SJYHP SNE SOJ SRMVM SSLCW UOJIU UTJUX ZMTXR 2JN AAYXX ABBRH ABDBE ABFSG ABRTQ ACSTC ADKFA AEZWR AFDZB AFFHD AFHIU AFOHR AHPBZ AHWEU AIXLP ATHPR AYFIA CITATION KOV PHGZM PHGZT PQGLB 8FE 8FG AZQEC DWQXO GNUQQ JQ2 P62 PKEHL PQEST PQQKQ PQUKI
ID	FETCH-LOGICAL-c1855-d570c4eae2d649da338153fce07c898e62c888e0f6e332515a60f7092d5b2e3e3
IEDL.DBID	RSV
ISSN	2661-8907 2662-995X
IngestDate	Wed Nov 05 15:00:34 EST 2025 Sat Nov 29 05:16:52 EST 2025 Fri Feb 21 02:46:10 EST 2025
IsPeerReviewed	true
IsScholarly	true
Issue	1
Keywords	Power distribution network Decoupling capacitance Side-channel attack
Language	English
LinkModel	DirectLink
MergedId	FETCHMERGED-LOGICAL-c1855-d570c4eae2d649da338153fce07c898e62c888e0f6e332515a60f7092d5b2e3e3
Notes	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ORCID	0000-0001-9950-2251
PQID	2921322596
PQPubID	6623307
ParticipantIDs	proquest_journals_2921322596 crossref_primary_10_1007_s42979_022_01491_5 springer_journals_10_1007_s42979_022_01491_5
PublicationCentury	2000
PublicationDate	2023-01-01
PublicationDateYYYYMMDD	2023-01-01
PublicationDate_xml	– month: 01 year: 2023 text: 2023-01-01 day: 01
PublicationDecade	2020
PublicationPlace	Singapore
PublicationPlace_xml	– name: Singapore – name: Kolkata
PublicationTitle	SN computer science
PublicationTitleAbbrev	SN COMPUT. SCI
PublicationYear	2023
Publisher	Springer Nature Singapore Springer Nature B.V
Publisher_xml	– name: Springer Nature Singapore – name: Springer Nature B.V
References	Tang KT, Friedman EG. Transient IR voltage drops in CMOS-based power distribution networks. In: Proceedings of the 43rd IEEE Midwest symposium on circuits and systems (Cat.No.CH37144), vol. 3; 2000. p. 1396–9. Coron JS, Kizhvatov I. An efficient method for random delay generation in embedded software. In: Cryptographic hardware and embedded systems—CHES 2009, 11th international workshop, Lausanne, Switzerland, September 6–9, 2009, Proceedings; 2009. p. 156–70. Ishai Y, Sahai A, Wagner DA. Private circuits: Securing hardware against probing attacks. In: Advances in cryptology—CRYPTO 2003, 23rd annual international cryptology conference, Santa Barbara, California, USA, August 17–21, 2003; 2003. p. 463–81. Bucci M, Giancane L, Luzzi R, Trifiletti A. Three-phase dual-rail pre-charge logic. In: Cryptographic hardware and embedded systems—CHES 2006, 8th international workshop, Yokohama, Japan, October 10–13, 2006, Proceedings; 2006. p. 232–41. MayhewMMuresanROn-chip nanoscale capacitor decoupling architectures for hardware securityIEEE Trans Emerg Top Comput20142141510.1109/TETC.2014.2303934 Tang KT, Friedman EG. Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2002;10(4):487–93. Selvam R, Tyagi A. Power side-channel resistance of RNS secure logic. In: 31st international conference on VLSI design and 17th international conference on embedded systems, VLSID 2018, Pune, India, January 6–10, 2018; 2018. p. 143–8. Mayhew M, Muresan R. Modeling the effect of nmos gate capacitance in an on-chip decoupling capacitor paa countermeasure. In: 2014 IEEE 57th international Midwest symposium on circuits and systems (MWSCAS); 2014. p. 121–4. Joo J, Sun Y, Lee J, Kong S, Kang S, Song I, Hwang C. Modeling of power supply noise associated with package parasitics in an on-chip ldo regulator. In: 2021 IEEE international joint EMC/SI/PI and EMC Europe symposium; 2021. p. 395–9. TanakaHMatsushimaTYanoYWadaOCompensating method of equivalent current sources of LSI-core macromodel considering voltage fluctuations in on-chip power distribution networkIEEE Trans Electromagn Compat.20226441250125610.1109/TEMC.2022.3155471 Benini L, Galati A, Macii A, Macii E, Poncino M. Energy-efficient data scrambling on memory-processor interfaces. In: Proceedings of the 2003 international symposium on low power electronics and design, 2003, Seoul, Korea, August 25–27, 2003; 2003. p. 26–9. Tiri K, Verbauwhede I. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: 2004 design, automation and test in Europe conference and exposition (DATE 2004), 16–20 February 2004, Paris, France; 2004. p. 246–51. Nikova S, Rechberger C, Rijmen V. Threshold implementations against side-channel attacks and glitches. In: Information and communications security, 8th international conference, ICICS 2006, Raleigh, NC, USA, December 4–7, 2006, Proceedings; 2006. p. 529–45. KenarangiFPartin-VaisbandIExploiting machine learning against on-chip power analysis attacks: tradeoffs and design considerationsIEEE Trans Circuits Syst I Regul Pap201966276978110.1109/TCSI.2018.2872567 MuresanROn-chip CMOS self-decoupling battery cell system for security protectionCan J Electr Comput Eng2020432839110.1109/CJECE.2019.2949934 Chari S, Rao JR, Rohatgi P. Template attacks. In: Cryptographic hardware and embedded systems—CHES 2002, 4th international workshop, Redwood Shores, CA, USA, August 13–15, 2002, revised papers; 2002. p. 13–28. Mao J, Kim W, Choi S, Swaminathan M, Libous J, O’connor D. Electromagnetic modelling of switching noise in on-chip power distribution networks. In: 8th international conference on electromagnetic interference and compatibility; 2003. p. 47–52. Kocher PC. Timing attacks on implementations of Diffie–Hellman, RSA, DSS, and other systems. In: Advances in cryptology—CRYPTO ’96, 16th annual international cryptology conference, Santa Barbara, California, USA, August 18–22, 1996, Proceedings, 1996. p. 104–13. Moradi A, Mischke O, Eisenbarth T. Correlation-enhanced power analysis collision attack. In: Cryptographic hardware and embedded systems, CHES 2010, 12th international workshop, Santa Barbara, CA, USA, August 17–20, 2010. Proceedings; 2010. p. 125–39. Tiri K, Verbauwhede I. Design method for constant power consumption of differential logic circuits. CoRR, abs/0710.4756; 2007. Selvam R, Tyagi A. Power distribution network capacitive decoupling for side-channel resistance. In: 2021 IEEE international symposium on smart electronic systems (iSES); 2021. p. 183–8. Dofe J, Yu Q. Exploiting PDN noise to thwart correlation power analysis attacks in 3d ics. In: Proceedings of the 20th system level interconnect prediction workshop, SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018; 2018. p. 6:1–6. 1491_CR3 1491_CR20 1491_CR4 1491_CR5 1491_CR11 1491_CR6 1491_CR10 1491_CR7 1491_CR13 H Tanaka (1491_CR15) 2022; 64 1491_CR8 1491_CR12 1491_CR9 1491_CR14 1491_CR17 1491_CR16 1491_CR18 F Kenarangi (1491_CR21) 2019; 66 R Muresan (1491_CR22) 2020; 43 M Mayhew (1491_CR19) 2014; 2 1491_CR1 1491_CR2
References_xml	– reference: Ishai Y, Sahai A, Wagner DA. Private circuits: Securing hardware against probing attacks. In: Advances in cryptology—CRYPTO 2003, 23rd annual international cryptology conference, Santa Barbara, California, USA, August 17–21, 2003; 2003. p. 463–81. – reference: Dofe J, Yu Q. Exploiting PDN noise to thwart correlation power analysis attacks in 3d ics. In: Proceedings of the 20th system level interconnect prediction workshop, SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018; 2018. p. 6:1–6. – reference: Selvam R, Tyagi A. Power side-channel resistance of RNS secure logic. In: 31st international conference on VLSI design and 17th international conference on embedded systems, VLSID 2018, Pune, India, January 6–10, 2018; 2018. p. 143–8. – reference: Selvam R, Tyagi A. Power distribution network capacitive decoupling for side-channel resistance. In: 2021 IEEE international symposium on smart electronic systems (iSES); 2021. p. 183–8. – reference: Joo J, Sun Y, Lee J, Kong S, Kang S, Song I, Hwang C. Modeling of power supply noise associated with package parasitics in an on-chip ldo regulator. In: 2021 IEEE international joint EMC/SI/PI and EMC Europe symposium; 2021. p. 395–9. – reference: TanakaHMatsushimaTYanoYWadaOCompensating method of equivalent current sources of LSI-core macromodel considering voltage fluctuations in on-chip power distribution networkIEEE Trans Electromagn Compat.20226441250125610.1109/TEMC.2022.3155471 – reference: Nikova S, Rechberger C, Rijmen V. Threshold implementations against side-channel attacks and glitches. In: Information and communications security, 8th international conference, ICICS 2006, Raleigh, NC, USA, December 4–7, 2006, Proceedings; 2006. p. 529–45. – reference: Mayhew M, Muresan R. Modeling the effect of nmos gate capacitance in an on-chip decoupling capacitor paa countermeasure. In: 2014 IEEE 57th international Midwest symposium on circuits and systems (MWSCAS); 2014. p. 121–4. – reference: Tang KT, Friedman EG. Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2002;10(4):487–93. – reference: MayhewMMuresanROn-chip nanoscale capacitor decoupling architectures for hardware securityIEEE Trans Emerg Top Comput20142141510.1109/TETC.2014.2303934 – reference: Benini L, Galati A, Macii A, Macii E, Poncino M. Energy-efficient data scrambling on memory-processor interfaces. In: Proceedings of the 2003 international symposium on low power electronics and design, 2003, Seoul, Korea, August 25–27, 2003; 2003. p. 26–9. – reference: Bucci M, Giancane L, Luzzi R, Trifiletti A. Three-phase dual-rail pre-charge logic. In: Cryptographic hardware and embedded systems—CHES 2006, 8th international workshop, Yokohama, Japan, October 10–13, 2006, Proceedings; 2006. p. 232–41. – reference: Tang KT, Friedman EG. Transient IR voltage drops in CMOS-based power distribution networks. In: Proceedings of the 43rd IEEE Midwest symposium on circuits and systems (Cat.No.CH37144), vol. 3; 2000. p. 1396–9. – reference: MuresanROn-chip CMOS self-decoupling battery cell system for security protectionCan J Electr Comput Eng2020432839110.1109/CJECE.2019.2949934 – reference: Kocher PC. Timing attacks on implementations of Diffie–Hellman, RSA, DSS, and other systems. In: Advances in cryptology—CRYPTO ’96, 16th annual international cryptology conference, Santa Barbara, California, USA, August 18–22, 1996, Proceedings, 1996. p. 104–13. – reference: KenarangiFPartin-VaisbandIExploiting machine learning against on-chip power analysis attacks: tradeoffs and design considerationsIEEE Trans Circuits Syst I Regul Pap201966276978110.1109/TCSI.2018.2872567 – reference: Coron JS, Kizhvatov I. An efficient method for random delay generation in embedded software. In: Cryptographic hardware and embedded systems—CHES 2009, 11th international workshop, Lausanne, Switzerland, September 6–9, 2009, Proceedings; 2009. p. 156–70. – reference: Mao J, Kim W, Choi S, Swaminathan M, Libous J, O’connor D. Electromagnetic modelling of switching noise in on-chip power distribution networks. In: 8th international conference on electromagnetic interference and compatibility; 2003. p. 47–52. – reference: Moradi A, Mischke O, Eisenbarth T. Correlation-enhanced power analysis collision attack. In: Cryptographic hardware and embedded systems, CHES 2010, 12th international workshop, Santa Barbara, CA, USA, August 17–20, 2010. Proceedings; 2010. p. 125–39. – reference: Tiri K, Verbauwhede I. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: 2004 design, automation and test in Europe conference and exposition (DATE 2004), 16–20 February 2004, Paris, France; 2004. p. 246–51. – reference: Tiri K, Verbauwhede I. Design method for constant power consumption of differential logic circuits. CoRR, abs/0710.4756; 2007. – reference: Chari S, Rao JR, Rohatgi P. Template attacks. In: Cryptographic hardware and embedded systems—CHES 2002, 4th international workshop, Redwood Shores, CA, USA, August 13–15, 2002, revised papers; 2002. p. 13–28. – ident: 1491_CR1 doi: 10.1007/3-540-68697-5_9 – ident: 1491_CR16 doi: 10.1109/TVLSI.2002.800533 – ident: 1491_CR8 doi: 10.1109/VLSID.2018.52 – volume: 66 start-page: 769 issue: 2 year: 2019 ident: 1491_CR21 publication-title: IEEE Trans Circuits Syst I Regul Pap doi: 10.1109/TCSI.2018.2872567 – ident: 1491_CR3 doi: 10.1007/978-3-642-15031-9_9 – ident: 1491_CR6 doi: 10.1007/978-3-540-45146-4_27 – ident: 1491_CR14 doi: 10.1109/ICEMIC.2003.237781 – ident: 1491_CR9 doi: 10.1007/11894063_19 – ident: 1491_CR12 doi: 10.1109/iSES52644.2021.00051 – ident: 1491_CR17 doi: 10.1109/EMC/SI/PI/EMCEurope52599.2021.9559151 – ident: 1491_CR13 doi: 10.1109/MWSCAS.2000.951474 – volume: 2 start-page: 4 issue: 1 year: 2014 ident: 1491_CR19 publication-title: IEEE Trans Emerg Top Comput doi: 10.1109/TETC.2014.2303934 – volume: 43 start-page: 83 issue: 2 year: 2020 ident: 1491_CR22 publication-title: Can J Electr Comput Eng doi: 10.1109/CJECE.2019.2949934 – ident: 1491_CR4 doi: 10.1007/978-3-642-04138-9_12 – ident: 1491_CR10 – ident: 1491_CR11 – ident: 1491_CR2 doi: 10.1007/3-540-36400-5_3 – ident: 1491_CR7 doi: 10.1007/11935308_38 – volume: 64 start-page: 1250 issue: 4 year: 2022 ident: 1491_CR15 publication-title: IEEE Trans Electromagn Compat. doi: 10.1109/TEMC.2022.3155471 – ident: 1491_CR18 doi: 10.1109/MWSCAS.2014.6908367 – ident: 1491_CR5 doi: 10.1145/871506.871517 – ident: 1491_CR20 doi: 10.1145/3225209.3225212
SSID	ssj0002504465
Score	2.2052777
Snippet	Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to...
SourceID	proquest crossref springer
SourceType	Aggregation Database Index Database Publisher
StartPage	77
SubjectTerms	Algorithms Capacitance Circuit design Computer Imaging Computer Science Computer Systems Organization and Communication Networks Data integrity Data Structures and Information Theory Decoupling Design Discriminant analysis Electric power distribution Information Systems and Communication Service Integrated circuits Machine learning Original Research Pattern Recognition and Graphics Propagation Smart and Connected Electronic Systems Software Engineering/Programming and Operating Systems Topology Vision
SummonAdditionalLinks	– databaseName: Advanced Technologies & Aerospace Database dbid: P5Z link: http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwpV3NS8MwFA86PXjxAxWnU3LwpsE2adrmJGObeJA5UMf0Utok1YJ0cx_-_eal6YaCXjy3hPDey_tK3u-H0DljioWS-QSYF0mQMU2EylISZ0YlqQzC2E54D--ifj8ejcTANdxm7lll7ROto1ZjCT3yKyooFE5chNeTDwKsUXC76ig01tEGoCQAdcOAvyx7LADPFVg2SROGKBGCj9zcjJ2eM644EgSes0OdYLb7PTatEs4fd6Q29Nzs_HfTu2jbJZ24XVnJHlrT5T56buOHQmkC8wWlfse9Je43Huf4viTyrZjgoVK4C-C6jhcL96t34xgauLhritcFzPS-4o6JurKYgxEdoKeb3mPnljiiBSJNuOZE8ciTgU41VWEgVGrKVuMIc6m9SMYi1iGVplDWXh5qxkxCxNPQyyNPUMUzqplmh6hRjkt9hLDK_MwXmalzYEUJYEDGbfhxlJr_c0Gb6KIWcTKp8DSSJXKyVUhiFJJYhSS8iVq1XBN3tmbJSqhNdFlrZvX599WO_17tBG0Bl3zVX2mhxny60KdoU37Oi9n0zFrWF78X0aA priority: 102 providerName: ProQuest
Title	A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance
URI	https://link.springer.com/article/10.1007/s42979-022-01491-5 https://www.proquest.com/docview/2921322596
Volume	4
hasFullText	1
inHoldings	1
isFullTextHit
isPrint
journalDatabaseRights	– providerCode: PRVPQU databaseName: Advanced Technologies & Aerospace Database customDbUrl: eissn: 2661-8907 dateEnd: 20241213 omitProxy: false ssIdentifier: ssj0002504465 issn: 2661-8907 databaseCode: P5Z dateStart: 20200101 isFulltext: true titleUrlDefault: https://search.proquest.com/hightechjournals providerName: ProQuest – providerCode: PRVPQU databaseName: Computer Science Database customDbUrl: eissn: 2661-8907 dateEnd: 20241213 omitProxy: false ssIdentifier: ssj0002504465 issn: 2661-8907 databaseCode: K7- dateStart: 20200101 isFulltext: true titleUrlDefault: http://search.proquest.com/compscijour providerName: ProQuest – providerCode: PRVPQU databaseName: ProQuest Central customDbUrl: eissn: 2661-8907 dateEnd: 20241213 omitProxy: false ssIdentifier: ssj0002504465 issn: 2661-8907 databaseCode: BENPR dateStart: 20200101 isFulltext: true titleUrlDefault: https://www.proquest.com/central providerName: ProQuest – providerCode: PRVAVX databaseName: SpringerLINK Contemporary 1997-Present customDbUrl: eissn: 2661-8907 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0002504465 issn: 2661-8907 databaseCode: RSV dateStart: 20190101 isFulltext: true titleUrlDefault: https://link.springer.com/search?facet-content-type=%22Journal%22 providerName: Springer Nature – providerCode: PRVAVX databaseName: SpringerLINK Contemporary 1997-Present customDbUrl: eissn: 2661-8907 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0002504465 issn: 2661-8907 databaseCode: RSV dateStart: 20200101 isFulltext: true titleUrlDefault: https://link.springer.com/search?facet-content-type=%22Journal%22 providerName: Springer Nature
link	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV07T8MwED5By8BCeYpCqTywgaUkjpN4LH0ICRSqFqrCEiW2A5FQWvXB78fOqwLBAEuWOKfofL6X7-4DuCREEIcTE2vkRWxHRGImohB7kdqSkNuOl3V4T-5d3_emUzYsmsKWZbV7eSWZaeqq2U1pTpdhXX2u3XpFfRvqytx5GrBhNJ5UmRU9lMt2aNEh8_OnX63QxrX8dhuaGZlB43-_tw97hVOJOrkUHMCWTA-hUQI2oOL8HsFzB40TIbFuKUjlO-pXo77RLEYPKeZvyRxNhEA9PU-3gMJCfl4qjnTOFvVUvLrWbbyvqKsMLU9WWm6O4WnQf-ze4gJbAXNloSkW1DW4LUNpCcdmIlSRqtJ9MZeGyz3mScfiKjaWRuxIQpQPREPHiF2DWYJGliSSnEAtnaXyFJCIzMhkkQptNEWu5_8oTWF6bqjWx8xqwlXJ62Cej9AIqmHJGdcCxbUg41pAm9AqtyMojtMysJilo2bKnCZcl-zfvP6d2tnflp_DroaTz1MsLaitFmt5ATv8Y5UsF22o3_T94agN23cuVs8hfWlnovcJXgjPVg
linkProvider	Springer Nature
linkToHtml	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMw1V1LSyNBEC58gV58sIrx2Qc9rc1OuufVBxExipKYXfBB9jTOdPdoQCbRRMU_5W-0ah4JCu7Nw55nKJiurx5fTVcVwI6URvpa1jltXuRuIi1XJol5mKBKYu36Yd7hfd0K2u2w01F_JuCt6oWha5WVT8wdtelpqpH_EkoQcfKUf9B_4LQ1iv6uVis0Clg07esLUrbB_lkD9bsrxMnx5dEpL7cKcI2xyePGCxzt2tgK47vKxMjR0OpTbZ1Ahyq0vtDICq2T-lZKjP5e7Dtp4ChhvERYaSXKnYRpV4YB2VUz4KOaDo0Dc_PtlRj2BFfK65R9Onm3Hrr-QHG6Pk-8BI_nYywcJ7if_snmoe5k4X87pEWYL5NqdlhYwRJM2OwH_D1kF11jOfVPZPaeHY_mmrNeyn5nXN91--zaGNag4cHl3i_WLu7FMypQswaS8yfqWb5lR5hV6O6QjGQZrr7la1ZgKutldhWYSepJXSXI40iipmFH6BbrYRDj-6kSNfhZqTTqF_NCotFk6BwAEQIgygEQeTXYqPQYlb5jEI2VWIO9Cgnjx19LW_u3tG2YPb08b0Wts3ZzHeYEZmtFLWkDpoaPT3YTZvTzsDt43MpRzeDmuxHyDtlILNg
linkToPdf	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwpV1LT8MwDLZgIMSF8RSDATlwg4i26SvHaQ-BmMakwTROUZukUAl109bx-0n6GiA4IM5N08p2Yjvx9xngkhBBXE5MrDsvYjskElMRBtgPlUoCbrt-hvAe973BwJ9M6PATij-rdi-vJHNMg2ZpStKbmYhuKuCb2kU9inUlug7x1ZfWYcPWhfQ6Xx-Nq1MWTdBlu06Blvn51a8eaRVmfrsZzRxOr_7_X92FnSLYRK3cOvZgTSb7UC8bOaBiXR_AcwuNYiGxhhok8g11KwpwNI3QQ4L5azxDYyFQR_PsFi2y0CAvIUf6LBd1VB671PDeF9RWDpjHqbanQ3jqdR_bt7jouYC58twOFo5ncFsG0hKuTUWgMli1J0ZcGh73qS9di6ucWRqRKwlRsZETuEbkGdQSTmhJIskR1JJpIo8BidAMTRqqlEfPyDUvkNpBTN8L1PiIWg24KuXOZjm1BqtIlDOpMSU1lkmNOQ1olqphxTJbMItaOpt2qNuA61IVq8e_z3byt-EXsDXs9Fj_bnB_Ctu643x-CtOEWjpfyjPY5O9pvJifZ9b3AZLq17Q
openUrl	ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+Side-Channel+Evaluation+of+On-chip+Vdd+Distribution+Network+with+Decoupling+Capacitance&rft.jtitle=SN+computer+science&rft.au=Selvam%2C+Ravikumar&rft.au=Tyagi%2C+Akhilesh&rft.date=2023-01-01&rft.issn=2661-8907&rft.eissn=2661-8907&rft.volume=4&rft.issue=1&rft_id=info:doi/10.1007%2Fs42979-022-01491-5&rft.externalDBID=n%2Fa&rft.externalDocID=10_1007_s42979_022_01491_5
thumbnail_l	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2661-8907&client=summon
thumbnail_m	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2661-8907&client=summon
thumbnail_s	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2661-8907&client=summon