A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance

Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target o...

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Vydané v:	SN computer science Ročník 4; číslo 1; s. 77
Hlavní autori:	Selvam, Ravikumar, Tyagi, Akhilesh
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Singapore Springer Nature Singapore 01.01.2023 Springer Nature B.V
Predmet:	Algorithms Capacitance Circuit design Computer Imaging Computer Science Computer Systems Organization and Communication Networks Data integrity Data Structures and Information Theory Decoupling Design Discriminant analysis Electric power distribution Information Systems and Communication Service Integrated circuits Machine learning Original Research Pattern Recognition and Graphics Propagation Smart and Connected Electronic Systems Software Engineering/Programming and Operating Systems Topology Vision Power distribution network Decoupling capacitance Side-channel attack
ISSN:	2661-8907, 2662-995X, 2661-8907
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Abstract	Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current ( I ) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance.
AbstractList	Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current (I) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance. Design of an on-chip power (Vdd) distribution network (PDN) is an important step in modern-day integrated circuit design. Several algorithms and tools exist to enhance the performance of power distribution with reduced noise. Unfortunately, however, power distribution network is the primary target of power analysis side-channels. In this paper, the values and topologies of decoupling capacitance incorporated into on-chip power distribution network are analyzed for side-channel resistance. We show that an on-chip power distribution network with decoupling capacitance thwarts the power side-channel attacks. The proposed design uses multiple decoupling capacitances along the power lanes in a distributed fashion to suppress the data leakage from the sensitive logic blocks. Grid-style and tree style power distribution networks are designed and evaluated to assess the effect of decoupling capacitance on power side-channel resistance. A novel, approximate heuristics to extract the feature vector from the switching current ( I ) of the internal logic blocks is developed and applied in the analysis. Machine learning (ML) classifiers are used to quantify the side-channel effectiveness in terms of success rate for the power side-channel adversary. The test circuit for proposed techniques is implemented using FreePDK 45 nm technology library. Spice level simulations are conducted with various decoupling capacitance values. With only 39.33% area overhead, the power side-channel adversary success rate is reduced from 83 to 21% for tree-style PDN and from 68 to 17% for grid-style PDN with decoupling capacitance.
ArticleNumber	77
Author	Tyagi, Akhilesh Selvam, Ravikumar
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References_xml	– reference: Ishai Y, Sahai A, Wagner DA. Private circuits: Securing hardware against probing attacks. In: Advances in cryptology—CRYPTO 2003, 23rd annual international cryptology conference, Santa Barbara, California, USA, August 17–21, 2003; 2003. p. 463–81. – reference: Dofe J, Yu Q. Exploiting PDN noise to thwart correlation power analysis attacks in 3d ics. In: Proceedings of the 20th system level interconnect prediction workshop, SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018; 2018. p. 6:1–6. – reference: Selvam R, Tyagi A. Power side-channel resistance of RNS secure logic. In: 31st international conference on VLSI design and 17th international conference on embedded systems, VLSID 2018, Pune, India, January 6–10, 2018; 2018. p. 143–8. – reference: Selvam R, Tyagi A. Power distribution network capacitive decoupling for side-channel resistance. In: 2021 IEEE international symposium on smart electronic systems (iSES); 2021. p. 183–8. – reference: Joo J, Sun Y, Lee J, Kong S, Kang S, Song I, Hwang C. Modeling of power supply noise associated with package parasitics in an on-chip ldo regulator. In: 2021 IEEE international joint EMC/SI/PI and EMC Europe symposium; 2021. p. 395–9. – reference: TanakaHMatsushimaTYanoYWadaOCompensating method of equivalent current sources of LSI-core macromodel considering voltage fluctuations in on-chip power distribution networkIEEE Trans Electromagn Compat.20226441250125610.1109/TEMC.2022.3155471 – reference: Nikova S, Rechberger C, Rijmen V. Threshold implementations against side-channel attacks and glitches. In: Information and communications security, 8th international conference, ICICS 2006, Raleigh, NC, USA, December 4–7, 2006, Proceedings; 2006. p. 529–45. – reference: Mayhew M, Muresan R. Modeling the effect of nmos gate capacitance in an on-chip decoupling capacitor paa countermeasure. In: 2014 IEEE 57th international Midwest symposium on circuits and systems (MWSCAS); 2014. p. 121–4. – reference: Tang KT, Friedman EG. Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2002;10(4):487–93. – reference: MayhewMMuresanROn-chip nanoscale capacitor decoupling architectures for hardware securityIEEE Trans Emerg Top Comput20142141510.1109/TETC.2014.2303934 – reference: Benini L, Galati A, Macii A, Macii E, Poncino M. Energy-efficient data scrambling on memory-processor interfaces. In: Proceedings of the 2003 international symposium on low power electronics and design, 2003, Seoul, Korea, August 25–27, 2003; 2003. p. 26–9. – reference: Bucci M, Giancane L, Luzzi R, Trifiletti A. Three-phase dual-rail pre-charge logic. In: Cryptographic hardware and embedded systems—CHES 2006, 8th international workshop, Yokohama, Japan, October 10–13, 2006, Proceedings; 2006. p. 232–41. – reference: Tang KT, Friedman EG. Transient IR voltage drops in CMOS-based power distribution networks. In: Proceedings of the 43rd IEEE Midwest symposium on circuits and systems (Cat.No.CH37144), vol. 3; 2000. p. 1396–9. – reference: MuresanROn-chip CMOS self-decoupling battery cell system for security protectionCan J Electr Comput Eng2020432839110.1109/CJECE.2019.2949934 – reference: Kocher PC. Timing attacks on implementations of Diffie–Hellman, RSA, DSS, and other systems. In: Advances in cryptology—CRYPTO ’96, 16th annual international cryptology conference, Santa Barbara, California, USA, August 18–22, 1996, Proceedings, 1996. p. 104–13. – reference: KenarangiFPartin-VaisbandIExploiting machine learning against on-chip power analysis attacks: tradeoffs and design considerationsIEEE Trans Circuits Syst I Regul Pap201966276978110.1109/TCSI.2018.2872567 – reference: Coron JS, Kizhvatov I. An efficient method for random delay generation in embedded software. In: Cryptographic hardware and embedded systems—CHES 2009, 11th international workshop, Lausanne, Switzerland, September 6–9, 2009, Proceedings; 2009. p. 156–70. – reference: Mao J, Kim W, Choi S, Swaminathan M, Libous J, O’connor D. Electromagnetic modelling of switching noise in on-chip power distribution networks. In: 8th international conference on electromagnetic interference and compatibility; 2003. p. 47–52. – reference: Moradi A, Mischke O, Eisenbarth T. Correlation-enhanced power analysis collision attack. In: Cryptographic hardware and embedded systems, CHES 2010, 12th international workshop, Santa Barbara, CA, USA, August 17–20, 2010. Proceedings; 2010. p. 125–39. – reference: Tiri K, Verbauwhede I. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: 2004 design, automation and test in Europe conference and exposition (DATE 2004), 16–20 February 2004, Paris, France; 2004. p. 246–51. – reference: Tiri K, Verbauwhede I. Design method for constant power consumption of differential logic circuits. CoRR, abs/0710.4756; 2007. – reference: Chari S, Rao JR, Rohatgi P. Template attacks. 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SubjectTerms	Algorithms Capacitance Circuit design Computer Imaging Computer Science Computer Systems Organization and Communication Networks Data integrity Data Structures and Information Theory Decoupling Design Discriminant analysis Electric power distribution Information Systems and Communication Service Integrated circuits Machine learning Original Research Pattern Recognition and Graphics Propagation Smart and Connected Electronic Systems Software Engineering/Programming and Operating Systems Topology Vision
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Title	A Side-Channel Evaluation of On-chip Vdd Distribution Network with Decoupling Capacitance
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