An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programme...

Full description

Bibliographic Details

Published in:	International Conference on Field-programmable Logic and Applications pp. 1 - 8
Main Authors:	Arcas-Abella, Oriol, Ndu, Geoffrey, Sonmez, Nehir, Ghasempour, Mohsen, Armejach, Adria, Navaridas, Javier, Wei Song, Mawer, John, Cristal, Adrian, Lujan, Mikel
Format:	Conference Proceeding
Language:	English
Published:	Technical University of Munich (TUM) 01.09.2014
Subjects:	Acceleration Field programmable gate arrays Hardware Hardware design languages Probes Sorting
ISSN:	1946-147X
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!