An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programme...

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Vydané v:	International Conference on Field-programmable Logic and Applications s. 1 - 8
Hlavní autori:	Arcas-Abella, Oriol, Ndu, Geoffrey, Sonmez, Nehir, Ghasempour, Mohsen, Armejach, Adria, Navaridas, Javier, Wei Song, Mawer, John, Cristal, Adrian, Lujan, Mikel
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	Technical University of Munich (TUM) 01.09.2014
Predmet:	Acceleration Field programmable gate arrays Hardware Hardware design languages Probes Sorting
ISSN:	1946-147X
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