Field-programmable gate array implementation of efficient deep neural network architecture

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with su...

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Vydáno v:International journal of electrical and computer engineering (Malacca, Malacca) Ročník 14; číslo 4; s. 3863
Hlavní autoři: Kumar Reddy, Pottipati Dileep, Ramanaiah, Kota Venkata
Médium: Journal Article
Jazyk:angličtina
Vydáno: 01.08.2024
ISSN:2088-8708, 2722-2578
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Abstract Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.
AbstractList Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.
Author Kumar Reddy, Pottipati Dileep
Ramanaiah, Kota Venkata
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