Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications

The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in err...

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Vydáno v:International journal of reconfigurable and embedded systems Ročník 14; číslo 2; s. 398
Hlavní autoři: Venkata Sudhakar, Chowdam, Potladurty, Suresh Babu, Karipireddy, Prasad Reddy
Médium: Journal Article
Jazyk:angličtina
Vydáno: 01.07.2025
ISSN:2089-4864, 2722-2608
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Shrnutí:The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the ripple carry adder (RCA), carry save adder (CSA), conditional sum adder (COSA), carry select adder (CSLA), and clock gating technique. The proposed multipliers are implemented in Verilog hardware description language (HDL) and simulated on the Xilinx VIVADO 2021.2 design tool with target platform Artix-7 AC701 FPGA. The simulation results found that unsigned and signed approximate multiplier power consumption was reduced by 13% and 18.18% respectively and enhanced accuracy.
ISSN:2089-4864
2722-2608
DOI:10.11591/ijres.v14.i2.pp398-411