APA (7th ed.) Citation

Venkata Sudhakar, C., Potladurty, S. B., & Karipireddy, P. R. (2025). Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications. International journal of reconfigurable and embedded systems, 14(2), 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411

Chicago Style (17th ed.) Citation

Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and Evaluation of Clock-gating-based Approximate Multiplier for Error-tolerant Applications." International Journal of Reconfigurable and Embedded Systems 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.

MLA (9th ed.) Citation

Venkata Sudhakar, Chowdam, et al. "Design and Evaluation of Clock-gating-based Approximate Multiplier for Error-tolerant Applications." International Journal of Reconfigurable and Embedded Systems, vol. 14, no. 2, 2025, p. 398, https://doi.org/10.11591/ijres.v14.i2.pp398-411.