Bufferless NoC router design for optical networks-on-chip
In large-scale tiled chip multiprocessors (TCMPs), network-on-chip (NoC) is a prevalent interconnect solution. The NoC router plays a crucial role in NoC architecture, and two primary types exist: buffered and bufferless. The latter offers a promising solution due to its streamlined design, reduced...
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| Published in: | Journal of optical communications |
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| Main Authors: | , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
10.12.2024
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| ISSN: | 0173-4911, 2191-6322 |
| Online Access: | Get full text |
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| Abstract | In large-scale tiled chip multiprocessors (TCMPs), network-on-chip (NoC) is a prevalent interconnect solution. The NoC router plays a crucial role in NoC architecture, and two primary types exist: buffered and bufferless. The latter offers a promising solution due to its streamlined design, reduced energy consumption, and hardware efficiency. This paper proposes a 2D 4 × 4 mesh NoC architecture with a novel bufferless NoC router design using XY routing algorithm. The proposed mesh network consists of routers and processing elements, with each router connected to its four adjacent peers (North, South, East, and West) and a single processing element. The proposed router design eliminates the input buffers, output buffers and crossbar switch. The novel bufferless NoC router architecture comprises of various functional blocks, including ejection and injection controllers and Data ranking based on port prioritization, and age incrementor which efficiently solves long critical path issues by dynamically changing the port priority and hence solves the deadlock issue. By leveraging efficient routing and prioritization mechanisms, the novel architecture facilitates the seamless flow of flits through the network. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages. Our results indicate that the proposed bufferless router can lead to significant area (30.3 %) reduction over the standard BLESS. |
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| AbstractList | In large-scale tiled chip multiprocessors (TCMPs), network-on-chip (NoC) is a prevalent interconnect solution. The NoC router plays a crucial role in NoC architecture, and two primary types exist: buffered and bufferless. The latter offers a promising solution due to its streamlined design, reduced energy consumption, and hardware efficiency. This paper proposes a 2D 4 × 4 mesh NoC architecture with a novel bufferless NoC router design using XY routing algorithm. The proposed mesh network consists of routers and processing elements, with each router connected to its four adjacent peers (North, South, East, and West) and a single processing element. The proposed router design eliminates the input buffers, output buffers and crossbar switch. The novel bufferless NoC router architecture comprises of various functional blocks, including ejection and injection controllers and Data ranking based on port prioritization, and age incrementor which efficiently solves long critical path issues by dynamically changing the port priority and hence solves the deadlock issue. By leveraging efficient routing and prioritization mechanisms, the novel architecture facilitates the seamless flow of flits through the network. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages. Our results indicate that the proposed bufferless router can lead to significant area (30.3 %) reduction over the standard BLESS. |
| Author | Naik, Mohan Kumar Shama, Sanjeev Parepalli, Ramanamma |
| Author_xml | – sequence: 1 givenname: Ramanamma surname: Parepalli fullname: Parepalli, Ramanamma organization: Department of ECE , 56965 New Horizon College of Engineering , Bengaluru , 560103 , India – sequence: 2 givenname: Sanjeev surname: Shama fullname: Shama, Sanjeev organization: Department of ECE , 56965 New Horizon College of Engineering , Bengaluru , 560103 , India – sequence: 3 givenname: Mohan Kumar surname: Naik fullname: Naik, Mohan Kumar organization: Department of Mechatronics , Mangalore Institute of Technology and Engineering , Mangalore , India |
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