Real Time FPGA Implementation of an Efficient High Speed Harris Corner Detection Algorithm Based on High-Level Synthesis
Computer vision systems use corner detection to identify features in an image. In applications such as motion detection, tracking, picture registration, and object recognition, corner detection is often one of the initial steps. In this paper, a real-time image processing system based on Harris corn...
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| Veröffentlicht in: | Engineering, technology & applied science research Jg. 13; H. 6; S. 12169 - 12174 |
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| Hauptverfasser: | , , , , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
05.12.2023
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| ISSN: | 2241-4487, 1792-8036 |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | Computer vision systems use corner detection to identify features in an image. In applications such as motion detection, tracking, picture registration, and object recognition, corner detection is often one of the initial steps. In this paper, a real-time image processing system based on Harris corner detection was designed and implemented using Zynq architecture and model-based design tools. The system was based on a development board containing the Zynq-7000 chip, which consists of a combination of FPGA and microprocessor, and the image taken with a high-resolution camera was processed in real-time by applying color conversion and Harris corner detection. The filter hardware designs used in the system were made using the HDL Coder tool in Matlab/Simulink without writing HDL code. The hardware that receives images from the camera was designed on a model-based basis with the Xilinx Vivado 2020. The HDL code that was implemented on the Xilinx ZedBoard using Vivado software was then validated to ensure real-time operation with the incoming video stream. The results achieved exhibited superiority compared to prior implementations in terms of area efficiency (reduced number of gates on the target FPGA) and speed performance on an identical target card. Using the rapid prototyping approach, two alternative hardware accelerator designs were created using various high-level synthesis tools. This design used less than 50% of the host FPGA's logic resources and was at least 30% faster than current implementations. |
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| ISSN: | 2241-4487 1792-8036 |
| DOI: | 10.48084/etasr.6406 |