A Flexible Heterogeneous Multi-Core Architecture

Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough...

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Bibliographic Details
Published in:	16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) pp. 13 - 24
Main Authors:	Pericas, M., Cristal, A., Cazorla, F.J., Gonzalez, R., Jimenez, D.A., Valero, M.
Format:	Conference Proceeding Publication
Language:	English
Published:	IEEE 01.09.2007 Institute of Electrical and Electronics Engineers (IEEE)
Subjects:	Application software Arquitectura de computadors Computer architecture Concurrent computing Delay Engines Informàtica Microarchitecture Multi-threading Multicore processing Multiprocessing systems Multiprocessors Parallel architectures Parallel processing Parallel processing (Electronic computers) Processament en paral·lel (Ordinadors) Reconfigurable architectures Simultaneous multithreading processors Throughput Yarn Àrees temàtiques de la UPC
ISBN:	0769529445, 9780769529448
ISSN:	1089-795X
Online Access:	Get full text
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