A Flexible Heterogeneous Multi-Core Architecture

Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) S. 13 - 24
Hauptverfasser:	Pericas, M., Cristal, A., Cazorla, F.J., Gonzalez, R., Jimenez, D.A., Valero, M.
Format:	Tagungsbericht Verlag
Sprache:	Englisch
Veröffentlicht:	IEEE 01.09.2007 Institute of Electrical and Electronics Engineers (IEEE)
Schlagworte:	Application software Arquitectura de computadors Computer architecture Concurrent computing Delay Engines Informàtica Microarchitecture Multi-threading Multicore processing Multiprocessing systems Multiprocessors Parallel architectures Parallel processing Parallel processing (Electronic computers) Processament en paral·lel (Ordinadors) Reconfigurable architectures Simultaneous multithreading processors Throughput Yarn Àrees temàtiques de la UPC
ISBN:	0769529445, 9780769529448
ISSN:	1089-795X
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!