Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity

Processing-in-memory (PIM) architectures mitigate the Von Neumann bottleneck by integrating computation units into memory arrays. Among PIM architectures, digital SRAMPIM has become a prominent approach, directly integrating digital logic within the SRAM array. However, the rigid crossbar architectu...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems S. 1
Hauptverfasser:	Duan, Cenlin, Yang, Jianlei, Wang, Yikun, Wang, Yiou, Qi, Yingjie, He, Xiaolin, Yan, Bonan, Wang, Xueyan, Jia, Xiaotao, Zhao, Weisheng
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	IEEE 2025
Schlagworte:	Accuracy Algorithm/Architecture Co-design Artificial intelligence Artificial neural networks Computational efficiency Computational modeling Computer architecture Hardware Hybrid-grained Sparsity Integrated circuit modeling Memory management Processing-In-Memory Redundancy SRAM-PIM
ISSN:	0278-0070, 1937-4151
Online-Zugang:	Volltext
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