Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
Processing-in-memory (PIM) architectures mitigate the Von Neumann bottleneck by integrating computation units into memory arrays. Among PIM architectures, digital SRAMPIM has become a prominent approach, directly integrating digital logic within the SRAM array. However, the rigid crossbar architectu...
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| Vydáno v: | IEEE transactions on computer-aided design of integrated circuits and systems s. 1 |
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2025
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| Abstract | Processing-in-memory (PIM) architectures mitigate the Von Neumann bottleneck by integrating computation units into memory arrays. Among PIM architectures, digital SRAMPIM has become a prominent approach, directly integrating digital logic within the SRAM array. However, the rigid crossbar architecture and full array activation pose challenges in efficiently utilizing value-level sparsity. Moreover, neural network models exhibit a high proportion of zero bits within non-zero values, which remain underutilized due to architectural constraints. To overcome these limitations, we present Dyadic Block PIM (DB-PIM), a groundbreaking algorithm-architecture co-design framework to harness both value-level and bit-level sparsity. At the algorithm level, our hybrid-grained pruning technique, combined with a novel sparsity pattern, enables effective sparsity management. Architecturally, DB-PIM incorporates a sparse network and customized digital SRAM-PIM macros, including input pre-processing unit (IPU), dyadic block multiply units (DBMUs), and Canonical Signed Digit (CSD)-based adder trees. It circumvents structured zero values in weights and bypasses unstructured zero bits within non-zero weights and block-wise all-zero bit columns in input features. As a result, the DBPIM framework skips a majority of unnecessary computations, thereby driving significant gains in computational efficiency. Experimental results demonstrate that our DB-PIM framework achieves up to 8.01× speedup and 85.28% energy savings, significantly boosting computational efficiency in digital SRAMPIM systems. |
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| AbstractList | Processing-in-memory (PIM) architectures mitigate the Von Neumann bottleneck by integrating computation units into memory arrays. Among PIM architectures, digital SRAMPIM has become a prominent approach, directly integrating digital logic within the SRAM array. However, the rigid crossbar architecture and full array activation pose challenges in efficiently utilizing value-level sparsity. Moreover, neural network models exhibit a high proportion of zero bits within non-zero values, which remain underutilized due to architectural constraints. To overcome these limitations, we present Dyadic Block PIM (DB-PIM), a groundbreaking algorithm-architecture co-design framework to harness both value-level and bit-level sparsity. At the algorithm level, our hybrid-grained pruning technique, combined with a novel sparsity pattern, enables effective sparsity management. Architecturally, DB-PIM incorporates a sparse network and customized digital SRAM-PIM macros, including input pre-processing unit (IPU), dyadic block multiply units (DBMUs), and Canonical Signed Digit (CSD)-based adder trees. It circumvents structured zero values in weights and bypasses unstructured zero bits within non-zero weights and block-wise all-zero bit columns in input features. As a result, the DBPIM framework skips a majority of unnecessary computations, thereby driving significant gains in computational efficiency. Experimental results demonstrate that our DB-PIM framework achieves up to 8.01× speedup and 85.28% energy savings, significantly boosting computational efficiency in digital SRAMPIM systems. |
| Author | He, Xiaolin Wang, Xueyan Jia, Xiaotao Duan, Cenlin Yang, Jianlei Wang, Yiou Zhao, Weisheng Qi, Yingjie Wang, Yikun Yan, Bonan |
| Author_xml | – sequence: 1 givenname: Cenlin orcidid: 0000-0002-7531-3461 surname: Duan fullname: Duan, Cenlin organization: School of Integrated Circuit Science and Engineering, Fert Beijing Research Institute, Beihang University, Beijing, China – sequence: 2 givenname: Jianlei orcidid: 0000-0001-8424-7040 surname: Yang fullname: Yang, Jianlei email: jianlei@buaa.edu.cn organization: School of Computer Science and Engineering, Beihang University, Beijing, China – sequence: 3 givenname: Yikun surname: Wang fullname: Wang, Yikun organization: School of Computer Science and Engineering, Beihang University, Beijing, China – sequence: 4 givenname: Yiou surname: Wang fullname: Wang, Yiou organization: School of Computer Science and Engineering, Beihang University, Beijing, China – sequence: 5 givenname: Yingjie orcidid: 0009-0009-2785-4480 surname: Qi fullname: Qi, Yingjie organization: School of Computer Science and Engineering, Beihang University, Beijing, China – sequence: 6 givenname: Xiaolin surname: He fullname: He, Xiaolin organization: School of Computer Science and Engineering, Beihang University, Beijing, China – sequence: 7 givenname: Bonan orcidid: 0000-0002-3052-9330 surname: Yan fullname: Yan, Bonan organization: Institute for Artificial Intelligence, Peking University, Beijing, China – sequence: 8 givenname: Xueyan orcidid: 0000-0003-0080-4730 surname: Wang fullname: Wang, Xueyan organization: School of Integrated Circuit Science and Engineering, Fert Beijing Research Institute, Beihang University, Beijing, China – sequence: 9 givenname: Xiaotao orcidid: 0000-0003-2207-6092 surname: Jia fullname: Jia, Xiaotao organization: School of Integrated Circuit Science and Engineering, Fert Beijing Research Institute, Beihang University, Beijing, China – sequence: 10 givenname: Weisheng orcidid: 0000-0001-8088-0404 surname: Zhao fullname: Zhao, Weisheng email: weisheng.zhao@buaa.edu.cn organization: School of Integrated Circuit Science and Engineering, Fert Beijing Research Institute, Beihang University, Beijing, China |
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| Snippet | Processing-in-memory (PIM) architectures mitigate the Von Neumann bottleneck by integrating computation units into memory arrays. Among PIM architectures,... |
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| SubjectTerms | Accuracy Algorithm/Architecture Co-design Artificial intelligence Artificial neural networks Computational efficiency Computational modeling Computer architecture Hardware Hybrid-grained Sparsity Integrated circuit modeling Memory management Processing-In-Memory Redundancy SRAM-PIM |
| Title | Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity |
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