APA (7th ed.) Citation

Lustig, D., Sethi, G., Bhattacharjee, A., & Martonosi, M. (2017, June 14). Transistency Models: Memory Ordering at the Hardware-OS Interface. IEEE MICRO, 1. https://doi.org/10.1109/MM.2017.265090228

Chicago Style (17th ed.) Citation

Lustig, Daniel, Geet Sethi, Abhishek Bhattacharjee, and Margaret Martonosi. "Transistency Models: Memory Ordering at the Hardware-OS Interface." IEEE MICRO 14 Jun. 2017: 1. https://doi.org/10.1109/MM.2017.265090228.

MLA (9th ed.) Citation

Lustig, Daniel, et al. "Transistency Models: Memory Ordering at the Hardware-OS Interface." IEEE MICRO, 14 Jun. 2017, p. 1, https://doi.org/10.1109/MM.2017.265090228.