Lustig, D., Sethi, G., Bhattacharjee, A., & Martonosi, M. (2017, June 14). Transistency Models: Memory Ordering at the Hardware-OS Interface. IEEE MICRO, 1. https://doi.org/10.1109/MM.2017.265090228
Citace podle Chicago (17th ed.)Lustig, Daniel, Geet Sethi, Abhishek Bhattacharjee, a Margaret Martonosi. "Transistency Models: Memory Ordering at the Hardware-OS Interface." IEEE MICRO 14 Jun. 2017: 1. https://doi.org/10.1109/MM.2017.265090228.
Citace podle MLA (9th ed.)Lustig, Daniel, et al. "Transistency Models: Memory Ordering at the Hardware-OS Interface." IEEE MICRO, 14 Jun. 2017, p. 1, https://doi.org/10.1109/MM.2017.265090228.
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