APA (7th ed.) Citation

Maeda, N., Kaneko, M., Tanaka, H., & Kimoto, T. (2025). First-order SPICE modeling of SiC p- and n-channel side-gate JFETs toward high-temperature complementary JFET ICs. APL Electronic Devices, 1(2), . https://doi.org/10.1063/5.0254971

Chicago Style (17th ed.) Citation

Maeda, Noriyuki, Mitsuaki Kaneko, Hajime Tanaka, and Tsunenobu Kimoto. "First-order SPICE Modeling of SiC P- and N-channel Side-gate JFETs Toward High-temperature Complementary JFET ICs." APL Electronic Devices 1, no. 2 (2025). https://doi.org/10.1063/5.0254971.

MLA (9th ed.) Citation

Maeda, Noriyuki, et al. "First-order SPICE Modeling of SiC P- and N-channel Side-gate JFETs Toward High-temperature Complementary JFET ICs." APL Electronic Devices, vol. 1, no. 2, 2025, https://doi.org/10.1063/5.0254971.