The program decision logic approach to predicated execution

Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has...

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Published in:Proceedings of the 26th annual international symposium on Computer architecture pp. 208 - 219
Main Authors: August, David I., Sias, John W., Puiatti, Jean-Michel, Mahlke, Scott A., Connors, Daniel A., Crozier, Kevin M., Hwu, Wen-mei W.
Format: Conference Proceeding
Language:English
Published: Washington, DC, USA IEEE Computer Society 01.05.1999
Series:ACM Conferences
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ISBN:0769501702, 9780769501703
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Abstract Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has translated the programmer's original control structure directly into assembly code with conditional branch instructions. Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research. However, traditional branch handling techniques cannot significantly alter the program's inherent control structure. The advent of predication as a program control representation has enabled compilers to manipulate control in a form more closely related to the underlying program logic. This work takes full advantage of the predication paradigm by abstracting the program control flow into a logical form referred to as a program decision logic network. This network is modeled as a Boolean equation and minimized using modified versions of logic synthesis techniques. After minimization, the more efficient version of the program's original control flow is re-expressed in predicated code. Furthermore, this paper proposes extensions to the HPL PlayDoh predication model in support of more effective predicate decision logic network minimization. Finally, this paper shows the ability of the mechanisms presented to overcome limits on ILP previously imposed by rigid program control structure.
AbstractList Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has translated the programmer's original control structure directly into assembly code with conditional branch instructions. Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research. However, traditional branch handling techniques cannot significantly alter the program's inherent control structure. The advent of predication as a program control representation has enabled compilers to manipulate control in a form more closely related to the underlying program logic. This work takes full advantage of the predication paradigm by abstracting the program control flow into a logical form referred to as a program decision logic network. This network is modeled as a Boolean equation and minimized using modified versions of logic synthesis techniques. After minimization, the more efficient version of the program's original control flow is re-expressed in predicated code. Furthermore, this paper proposes extensions to the HPL PlayDoh predication model in support of more effective predicate decision logic network minimization. Finally, this paper shows the ability of the mechanisms presented to overcome limits on ILP previously imposed by rigid program control structure.
Author August, David I.
Mahlke, Scott A.
Hwu, Wen-mei W.
Connors, Daniel A.
Sias, John W.
Crozier, Kevin M.
Puiatti, Jean-Michel
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  givenname: Wen-mei W.
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  fullname: Hwu, Wen-mei W.
  organization: Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign, IL
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Snippet Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW...
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SubjectTerms Hardware -- Electronic design automation -- Methodologies for EDA
Hardware -- Integrated circuits -- Logic circuits
Hardware -- Integrated circuits -- Logic circuits -- Arithmetic and datapath circuits
Hardware -- Integrated circuits -- Logic circuits -- Design modules and hierarchy
Software and its engineering -- Software notations and tools -- Compilers
Title The program decision logic approach to predicated execution
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