Performance-impact limited area fill synthesis

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the lay...

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Bibliographic Details
Published in:2003 40th Annual Conference Design Automation pp. 22 - 27
Main Authors: Chen, Yu, Gupta, Puneet, Kahng, Andrew B.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 02.06.2003
Series:ACM Conferences
Subjects:
Applied computing > Arts and humanities > Architecture (buildings) > Computer-aided design
Applied computing > Physical sciences and engineering > Engineering > Computer-aided design
Hardware > Electronic design automation > Physical design (EDA)
Theory of computation > Design and analysis of algorithms
VLSI manufacturability
linear programming
coupling capacitance extraction
signal delay
dummy fill problem
greedy method
ISBN:1581136889, 9781581136883
Online Access:Get full text
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