Automatic trace analysis for logic of constraints

Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language...

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Vydáno v:2003 40th Annual Conference Design Automation s. 460 - 465
Hlavní autoři: Chen, Xi, Hsieh, Harry, Balarin, Felice, Watanabe, Yosinori
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 02.06.2003
Edice:ACM Conferences
Témata:
Hardware > Hardware validation
Hardware > Hardware validation > Functional verification > Assertion checking
Software and its engineering > Software creation and management > Software verification and validation
Theory of computation > Semantics and reasoning > Program reasoning > Assertions
performance constraint
simulation checker
logic of constraints
trace analysis
ISBN:1581136889, 9781581136883
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Shrnutí:Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language, Logic Of Constraints (LOC), to analyze the simulation traces for functional and performance constraint violations. For many interesting formulas, the checkers exhibit linear time complexity and constant memory usage. We illustrate the usefulness and efficiency of this approach with large designs and traces.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1581136889
9781581136883
DOI:10.1145/775832.775952