Clock gating for power optimization in ASIC design cycle theory & practice

In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend desig...

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Bibliographic Details
Published in:Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) pp. 307 - 308
Main Authors: S, Jairam, Rao, Madhusudan, Srinivas, Jithendra, Vishwanath, Parimala, H, Udayakumar, Rao, Jagdish
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 11.08.2008
IEEE
Series:ACM Conferences
Subjects:
Application specific integrated circuits
ASIC
Character generation
Clocks
Design methodology
Design optimization
Dynamic voltage scaling
Electronic design automation and methodology
Hardware > Electronic design automation > Hardware description languages and compilation
Hardware > Electronic design automation > Logic synthesis > Circuit optimization
History
Logic
low power
optimization
RTL
SoC
Technological innovation
low power
ASIC
RTL
optimization
SoC
ISBN:9781605581095, 1605581097, 9781424486342, 1424486343
Online Access:Get full text
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Summary:In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design.
ISBN:9781605581095
1605581097
9781424486342
1424486343
DOI:10.1145/1393921.1394003