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Citace podle MLA (9th ed.)S, Jairam, et al. "Clock Gating for Power Optimization in ASIC Design Cycle Theory & Practice." Proceeding of the 13th International Symposium on Low Power Electronics and Design (ISLPED '08), 11 Aug. 2008, pp. 307-308, https://doi.org/10.1145/1393921.1394003.