Definitive Guide to the ARM Cortex-M3 (2nd Edition)
This book is intended for hardware and software engineers, programmers, embedded product designers, system-on-chip engineers, electronics enthusiasts, academic researchers, and others who are investigating the Cortex-M3 processor. This user's guide does far more than simply outline the ARM Cort...
Uložené v:
| Hlavný autor: | |
|---|---|
| Médium: | E-kniha Kniha |
| Jazyk: | English |
| Vydavateľské údaje: |
Amsterdam
Elsevier
2010
Newnes is an imprint of Elsevier Elsevier Science & Technology Newnes |
| Vydanie: | 2 |
| Predmet: | |
| ISBN: | 185617963X, 9781856179638 |
| On-line prístup: | Získať plný text |
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- Title Page Conventions Terms and Abbreviations Preface Table of Contents 1. Introduction 2. Overview of the Cortex-M3 3. Cortex-M3 Basics 4. Instruction Sets 5. Memory Systems 6. Cortex-M3 Implementation Overview 7. Exceptions 8. The Nested Vectored Interrupt Controller and Interrupt Control 9. Interrupt Behavior 10. Cortex-M3 Programming 11. Exception Programming 12. Advanced Programming Features and System Behavior 13. The Memory Protection Unit 14. Other Cortex-M3 Features 15. Debug Architecture 16. Debugging Components 17. Getting Started with the Cortex-M3 Processor 18. Porting Applications from the ARM7 to the Cortex-M3 19. Starting Cortex-M3 Development Using the GNU Tool Chain 20. Getting Started with the Keil RealView Microcontroller Development Kit 21. Programming the Cortex-M3 Microcontrollers in NI LabVIEW Appendices References Index
- 15.2.1 Processor Debugging Interface -- 15.2.2 The Debug Host Interface -- 15.2.3 DP Module, AP Module, and DAP -- 15.2.4 Trace Interface -- 15.2.5 CoreSight Characteristics -- 15.3 Debug Modes -- 15.4 Debugging Events -- 15.5 Breakpoint in the Cortex-M3 -- 15.6 Accessing Register Content in Debug -- 15.7 Other Core Debugging Features -- Chapter 16. Debugging Components -- 16.1 Introduction -- 16.1.1 The Trace System in the Cortex-M3 -- 16.2 Trace Components: DWT -- 16.3 Trace Components: ITM -- 16.3.1 Software Trace with the ITM -- 16.3.2 Hardware Trace with ITM and DWT -- 16.3.3 ITM Timestamp -- 16.4 Trace Components: ETM -- 16.5 Trace Components: TPIU -- 16.6 The Flash Patch and Breakpoint Unit -- 16.6.1 Breakpoint Feature -- 16.6.2 Flash Patch Feature -- 16.6.3 Comparators -- 16.7 The Advanced High-Performance Bus Access Port -- 16.8 ROM Table -- Chapter 17. Getting Started with the Cortex-M3 Processor -- 17.1 Choosing a Cortex-M3 Product -- 17.2 Development Tools -- 17.2.1 C Compiler and Debuggers -- 17.2.2 Embedded OS Support -- 17.3 Differences between the Cortex-M3 Revision 0 and Revision 1 -- 17.3.1 Revision 1 Change: Moving from JTAG-DP to SWJ-DP -- 17.4 Differences between the Cortex-M3 Revision 1 and Revision 2 -- 17.4.1 Default Configuration of Double Word Stack Alignment -- 17.4.2 Auxiliary Control Register -- 17.4.3 ID Register Values Updates -- 17.4.4 Debug Features -- 17.4.5 Sleep Features -- 17.5 Benefits and Effects of the Revision 2 New Features -- 17.6 Differences between the Cortex-M3 and Cortex-M0 -- 17.6.1 Programmer's Model -- 17.6.2 Exceptions and NVIC -- 17.6.3 Instruction Set -- 17.6.4 Memory System Features -- 17.6.5 Debug Features -- 17.6.6 Compatibility -- Chapter 18. Porting Applications from the ARM7 to the Cortex-M3 -- 18.1 Overview -- 18.2 System Characteristics -- 18.2.1 Memory Map -- 18.2.2 Interrupts
- 18.2.3 MPU
- Front Cover -- Half Title Page -- The Definitive Guide to the ARM Cortex-M3 -- Copyright Page -- Table of Contents -- Foreword -- Foreword -- Preface -- Acknowledgments -- Conventions -- Terms and Abbreviations -- Chapter 1. Introduction -- 1.1 What Is the ARM Cortex-M3 Processor? -- 1.2 Background of ARM and ARM Architecture -- 1.2.1 A Brief History -- 1.2.2 Architecture Versions -- 1.2.3 Processor Naming -- 1.3 Instruction Set Development -- 1.4 The Thumb-2 Technology and Instruction Set Architecture -- 1.5 Cortex-M3 Processor Applications -- 1.6 Organization of This Book -- 1.7 Further Reading -- Chapter 2. Overview of the Cortex-M3 -- 2.1 Fundamentals -- 2.2 Registers -- 2.2.1 R0-R12: General-Purpose Registers -- 2.2.2 R13: Stack Pointers -- 2.2.3 R14: The Link Register -- 2.2.4 R15: The Program Counter -- 2.2.5 Special Registers -- 2.3 Operation Modes -- 2.4 The Built-In Nested Vectored Interrupt Controller -- 2.4.1 Nested Interrupt Support -- 2.4.2 Vectored Interrupt Support -- 2.4.3 Dynamic Priority Changes Support -- 2.4.4 Reduction of Interrupt Latency -- 2.4.5 Interrupt Masking -- 2.5 The Memory Map -- 2.6 The Bus Interface -- 2.7 The MPU -- 2.8 The Instruction Set -- 2.9 Interrupts and Exceptions -- 2.9.1 Low Power and High Energy Efficiency -- 2.10 Debugging Support -- 2.11 Characteristics Summary -- 2.11.1 High Performance -- 2.11.2 Advanced Interrupt-Handling Features -- 2.11.3 Low Power Consumption -- 2.11.4 System Features -- 2.11.5 Debug Supports -- Chapter 3. Cortex-M3 Basics -- 3.1 Registers -- 3.1.1 General Purpose Registers R0 through R7 -- 3.1.2 General Purpose Registers R8 through R12 -- 3.1.3 Stack Pointer R13 -- 3.1.4 Link Register R14 -- 3.1.5 Program Counter R15 -- 3.2 Special Registers -- 3.2.1 Program Status Registers -- 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers -- 3.2.3 The Control Register
- 10.3.3 Accessing Memory-Mapped Registers in C -- 10.3.4 Intrinsic Functions -- 10.3.5 Embedded Assembler and Inline Assembler -- 10.4 CMSIS -- 10.4.1 Background of CMSIS -- 10.4.2 Areas of Standardization -- 10.4.3 Organization of CMSIS -- 10.4.4 Using CMSIS -- 10.4.5 Benefits of CMSIS -- 10.5 Using Assembly -- 10.5.1 The Interface between Assembly and C -- 10.5.2 The First Step in Assembly Programming -- 10.5.3 Producing Outputs -- 10.5.4 The "Hello World" Example -- 10.5.5 Using Data Memory -- 10.6 Using Exclusive Access for Semaphores -- 10.7 Using Bit Band for Semaphores -- 10.8 Working with Bit Field Extract and Table Branch -- Chapter 11. Exception Programming -- 11.1 Using Interrupts -- 11.1.1 Stack Setup -- 11.1.2 Vector Table Setup -- 11.1.3 Interrupt Priority Setup -- 11.1.4 Enable the Interrupt -- 11.2 Exception/Interrupt Handlers -- 11.3 Software Interrupts -- 11.4 Example of Vector Table Relocation -- 11.5 Using SVC -- 11.6 SVC Example: Use for Text Message Output Functions -- 11.7 Using SVC with C -- Chapter 12. Advanced Programming Features and System Behavior -- 12.1 Running a System with Two Separate Stacks -- 12.2 Double-Word Stack Alignment -- 12.3 Nonbase Thread Enable -- 12.4 Performance Considerations -- 12.5 Lockup Situations -- 12.5.1 What Happens During Lockup? -- 12.5.2 Avoiding Lockup -- 12.6 FAULTMASK -- Chapter 13. The Memory Protection Unit -- 13.1 Overview -- 13.2 MPU Registers -- 13.3 Setting Up the MPU -- 13.4 Typical Setup -- 13.4.1 Example Use of the Subregion Disable -- Chapter 14. Other Cortex-M3 Features -- 14.1 The SYSTICK Timer -- 14.2 Power Management -- 14.2.1 Sleep Modes -- 14.2.2 Sleep-On-Exit Feature -- 14.2.3 Wakeup Interrupt Controller -- 14.3 Multiprocessor Communication -- 14.4 Self-Reset Control -- Chapter 15. Debug Architecture -- 15.1 Debugging Features Overview -- 15.2 CoreSight Overview
- 6.3 Bus Interfaces on the Cortex-M3 -- 6.3.1 The I-Code Bus -- 6.3.2 The D-Code Bus -- 6.3.3 The System Bus -- 6.3.4 The External PPB -- 6.3.5 The DAP Bus -- 6.4 Other Interfaces on the Cortex-M3 -- 6.5 The External PPB -- 6.6 Typical Connections -- 6.7 Reset Types and Reset Signals -- Chapter 7. Exceptions -- 7.1 Exception Types -- 7.2 Definitions of Priority -- 7.3 Vector Tables -- 7.4 Interrupt Inputs and Pending Behavior -- 7.5 Fault Exceptions -- 7.5.1 Bus Faults -- 7.5.2 Memory Management Faults -- 7.5.3 Usage Faults -- 7.5.4 Hard Faults -- 7.5.5 Dealing with Faults -- 7.6 Supervisor Call and Pendable Service Call -- Chapter 8. The Nested Vectored Interrupt Controller and Interrupt Control -- 8.1 Nested Vectored Interrupt Controller Overview -- 8.2 The Basic Interrupt Configuration -- 8.2.1 Interrupt Enable and Clear Enable -- 8.2.2 Interrupt Set Pending and Clear Pending -- 8.2.3 Priority Levels -- 8.2.4 Active Status -- 8.2.5 PRIMASK and FAULTMASK Special Registers -- 8.2.6 The BASEPRI Special Register -- 8.2.7 Configuration Registers for Other Exceptions -- 8.3 Example Procedures in Setting Up an Interrupt -- 8.4 Software Interrupts -- 8.5 The SYSTICK Timer -- Chapter 9. Interrupt Behavior -- 9.1 Interrupt/Exception Sequences -- 9.1.1 Stacking -- 9.1.2 Vector Fetches -- 9.1.3 Register Updates -- 9.2 Exception Exits -- 9.3 Nested Interrupts -- 9.4 Tail-Chaining Interrupts -- 9.5 Late Arrivals -- 9.6 More on the Exception Return Value -- 9.7 Interrupt Latency -- 9.8 Faults Related to Interrupts -- 9.8.1 Stacking -- 9.8.2 Unstacking -- 9.8.3 Vector Fetches -- 9.8.4 Invalid Returns -- Chapter 10. Cortex-M3 Programming -- 10.1 Overview -- 10.2 A Typical Development Flow -- 10.3 Using C -- 10.3.1 Example of a Simple C Program Using RealView Development Site -- 10.3.2 Compile the Same Example Using Keil MDK-ARM
- 3.3 Operation Mode -- 3.4 Exceptions and Interrupts -- 3.5 Vector Tables -- 3.6 Stack Memory Operations -- 3.6.1 Basic Operations of the Stack -- 3.6.2 Cortex-M3 Stack Implementation -- 3.6.3 The Two-Stack Model in the Cortex-M3 -- 3.7 Reset Sequence -- Chapter 4. Instruction Sets -- 4.1 Assembly Basics -- 4.1.1 Assembler Language: Basic Syntax -- 4.1.2 Assembler Language: Use of Suffixes -- 4.1.3 Assembler Language: Unified Assembler Language -- 4.2 Instruction List -- 4.2.1 Unsupported Instructions -- 4.3 Instruction Descriptions -- 4.3.1 Assembler Language: Moving Data -- 4.3.2 LDR and ADR Pseudo-Instructions -- 4.3.3 Assembler Language: Processing Data -- 4.3.4 Assembler Language: Call and Unconditional Branch -- 4.3.5 Assembler Language: Decisions and Conditional Branches -- 4.3.6 Assembler Language: Combined Compare and Conditional Branch -- 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions -- 4.3.8 Assembly Language: Saturation Operations -- 4.4 Several Useful Instructions in the Cortex-M3 -- 4.4.1 MSR and MRS -- 4.4.2 More on the IF-THEN Instruction Block -- 4.4.3 SDIV and UDIV -- 4.4.4 REV, REVH, and REVSH -- 4.4.5 Reverse Bit -- 4.4.6 SXTB, SXTH, UXTB, and UXTH -- 4.4.7 Bit Field Clear and Bit Field Insert -- 4.4.8 UBFX and SBFX -- 4.4.9 LDRD and STRD -- 4.4.10 Table Branch Byte and Table Branch Halfword -- Chapter 5. Memory Systems -- 5.1 Memory System Features Overview -- 5.2 Memory Maps -- 5.3 Memory Access Attributes -- 5.4 Default Memory Access Permissions -- 5.5 Bit-Band Operations -- 5.5.1 Advantages of Bit-Band Operations -- 5.5.2 Bit-Band Operation of Different Data Sizes -- 5.5.3 Bit-Band Operations in C Programs -- 5.6 Unaligned Transfers -- 5.7 Exclusive Accesses -- 5.8 Endian Mode -- Chapter 6. Cortex-M3 Implementation Overview -- 6.1 The Pipeline -- 6.2 A Detailed Block Diagram