An FPGA-based Solution for Convolution Operation Acceleration

Hardware-based acceleration is an extensive attempt to facilitate many computationally-intensive mathematics operations. This paper proposes an FPGA-based architecture to accelerate the convolution operation - a complex and expensive computing step that appears in many Convolutional Neural Network m...

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Vydáno v:	arXiv.org
Hlavní autoři:	Trung Dinh Pham, Bao Gia Bach, Lam Trinh Luu, Minh Dinh Nguyen, Pham, Hai Duc, Khoa Bui Anh, Nguyen, Xuan Quang, Cuong Pham Quoc
Médium:	Paper
Jazyk:	angličtina
Vydáno:	Ithaca Cornell University Library, arXiv.org 09.06.2022
Témata:	Artificial neural networks Computer architecture Design standards Edge computing Field programmable gate arrays Microprocessors
ISSN:	2331-8422
On-line přístup:	Získat plný text
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