An FPGA-based Solution for Convolution Operation Acceleration

Hardware-based acceleration is an extensive attempt to facilitate many computationally-intensive mathematics operations. This paper proposes an FPGA-based architecture to accelerate the convolution operation - a complex and expensive computing step that appears in many Convolutional Neural Network m...

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Veröffentlicht in:	arXiv.org
Hauptverfasser:	Trung Dinh Pham, Bao Gia Bach, Lam Trinh Luu, Minh Dinh Nguyen, Pham, Hai Duc, Khoa Bui Anh, Nguyen, Xuan Quang, Cuong Pham Quoc
Format:	Paper
Sprache:	Englisch
Veröffentlicht:	Ithaca Cornell University Library, arXiv.org 09.06.2022
Schlagworte:	Artificial neural networks Computer architecture Design standards Edge computing Field programmable gate arrays Microprocessors
ISSN:	2331-8422
Online-Zugang:	Volltext
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