TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design

In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of convenient APIs that allow users to easily express flexible...

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Veröffentlicht in:	arXiv.org
Hauptverfasser:	Guo, Licheng, Yuze Chi, Lau, Jason, Song, Linghao, Tian, Xingyu, Khatti, Moazin, Qiao, Weikang, Wang, Jie, Ecenur Ustun, Fang, Zhenman, Zhang, Zhiru, Cong, Jason
Format:	Paper
Sprache:	Englisch
Veröffentlicht:	Ithaca Cornell University Library, arXiv.org 06.09.2022
Schlagworte:	Design optimization Floorplans Pipelining (computers) Resource utilization
ISSN:	2331-8422
Online-Zugang:	Volltext
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