Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current...

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Veröffentlicht in:VLSI Design Jg. 2012; H. 1; S. 93 - 106
Hauptverfasser: Jerbi, Khaled, Raulet, Mickaël, Déforges, Olivier, Abid, Mohamed
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York Hindawi Limiteds 01.01.2012
Hindawi Publishing Corporation
Hindawi Limited
Schlagworte:
Algorithms
Automation
Behavior
Coding
Computer programs
Computer Science
Engineering Sciences
FIFO
Hardware
MPEG encoders
Signal and Image Processing
Studies
Transformations
Video compression
Orcc compiler
Automatic transformation
MPEG-4 SP
Data flow computing
LAR
RVC-CAL
ISSN:1065-514X, 1563-5171
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Zusammenfassung:In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current MPEG coding technologies using a dataflow language called Cal Actor Language (CAL). CAL is associated with a set of tools to design dataflow applications and to generate hardware and software implementations. Before this work, the existing CAL hardware compilers did not support high-level features of the CAL. After presenting the main notions of the RVC standard, this paper introduces an automatic transformation process that analyses the non-compliant features and makes the required changes in the intermediate representation of the compiler while keeping the same behavior. Finally, the implementation results of the transformation on video and still image decoders are summarized. We show that the obtained results can largely satisfy the real time constraints for an embedded design on FPGA as we obtain a throughput of 73 FPS for MPEG 4 decoder and 34 FPS for coding and decoding process of the LAR coder using a video of CIF image size. This work resolves the main limitation of hardware generation from CAL designs.
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ISSN:1065-514X
1563-5171
DOI:10.1155/2012/298396