Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current...

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Veröffentlicht in:	VLSI Design Jg. 2012; H. 1; S. 93 - 106
Hauptverfasser:	Jerbi, Khaled, Raulet, Mickaël, Déforges, Olivier, Abid, Mohamed
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York Hindawi Limiteds 01.01.2012 Hindawi Publishing Corporation Hindawi Limited
Schlagworte:	Algorithms Automation Behavior Coding Computer programs Computer Science Engineering Sciences FIFO Hardware MPEG encoders Signal and Image Processing Studies Transformations Video compression Orcc compiler Automatic transformation MPEG-4 SP Data flow computing LAR RVC-CAL
ISSN:	1065-514X, 1563-5171
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Abstract	In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current MPEG coding technologies using a dataflow language called Cal Actor Language (CAL). CAL is associated with a set of tools to design dataflow applications and to generate hardware and software implementations. Before this work, the existing CAL hardware compilers did not support high-level features of the CAL. After presenting the main notions of the RVC standard, this paper introduces an automatic transformation process that analyses the non-compliant features and makes the required changes in the intermediate representation of the compiler while keeping the same behavior. Finally, the implementation results of the transformation on video and still image decoders are summarized. We show that the obtained results can largely satisfy the real time constraints for an embedded design on FPGA as we obtain a throughput of 73 FPS for MPEG 4 decoder and 34 FPS for coding and decoding process of the LAR coder using a video of CIF image size. This work resolves the main limitation of hardware generation from CAL designs.
AbstractList	In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of components that can be updated and standardized separately. MPEG RVC framework aims at providing a unified high-level specification of current MPEG coding technologies using a dataflow language called Cal Actor Language (CAL). CAL is associated with a set of tools to design dataflow applications and to generate hardware and software implementations. Before this work, the existing CAL hardware compilers did not support high-level features of the CAL. After presenting the main notions of the RVC standard, this paper introduces an automatic transformation process that analyses the non-compliant features and makes the required changes in the intermediate representation of the compiler while keeping the same behavior. Finally, the implementation results of the transformation on video and still image decoders are summarized. We show that the obtained results can largely satisfy the real time constraints for an embedded design on FPGA as we obtain a throughput of 73 FPS for MPEG 4 decoder and 34 FPS for coding and decoding process of the LAR coder using a video of CIF image size. This work resolves the main limitation of hardware generation from CAL designs.
Author	Mickael Raulet Mohamed Abid Olivier Deforges Khaled Jerbi
Author_xml	– sequence: 1 givenname: Khaled surname: Jerbi fullname: Jerbi, Khaled organization: IETR/INSA. UMR CNRS 6164 35043 Rennes France – sequence: 2 givenname: Mickaël surname: Raulet fullname: Raulet, Mickaël organization: IETR/INSA. UMR CNRS 6164 35043 Rennes France – sequence: 3 givenname: Olivier surname: Déforges fullname: Déforges, Olivier organization: IETR/INSA. UMR CNRS 6164 35043 Rennes France – sequence: 4 givenname: Mohamed surname: Abid fullname: Abid, Mohamed organization: CES Laboratory, National Engineering School of Sfax, 3038 Sfax Tunisia
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CitedBy_id	crossref_primary_10_1016_j_image_2013_08_013
Cites_doi	10.1109/MSP.2010.936032 10.1109/IDT.2008.4802494 10.1007/BF02997530 10.1007/s11265-009-0397-5 10.1109/TIT.1966.1053907 10.1109/FDL.2008.4641423 10.1109/TCSVT.2007.897112 10.1145/1730836.1730864 10.1109/SOCC.2007.4545462 10.1007/978-1-4020-8588-8 10.1109/TCSVT.2009.2031517 10.1109/MDT.2009.69 10.1109/ICCTD.2009.195 10.1007/978-1-4419-6345-1_3 10.1007/s11265‐009‐0390‐z 10.1145/1065579.1065737 10.1109/ICASSP.2012.6288199 10.1109/SIPS.2008.4671776 10.1109/FCCM.2006.28
ContentType	Journal Article
Copyright	Copyright © 2012 Khaled Jerbi et al. Copyright © 2012 Khaled Jerbi et al. Khaled Jerbi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Distributed under a Creative Commons Attribution 4.0 International License
Copyright_xml	– notice: Copyright © 2012 Khaled Jerbi et al. – notice: Copyright © 2012 Khaled Jerbi et al. Khaled Jerbi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. – notice: Distributed under a Creative Commons Attribution 4.0 International License
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Keywords	Orcc compiler Automatic transformation MPEG-4 SP Data flow computing LAR RVC-CAL
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References_xml	– reference: Brooks C. Lee E. Liu X. Neuendorer S. Zhao Y. HZ: PtolemyII—heterogeneous concurrent modeling and design in Java (Volume 1: introduction to ptolemyII) Technical Memorandum 2004 UCB/ERL M04/27 Berkeley, Calif, USA University of California – volume: 26 start-page: 8 issue: 4 year: 2009 end-page: 17 ident: 8 article-title: An introduction to high-level synthesis – reference: Mattavelli M. Janneck J. W. Raulet M. Bhattacharyya S. S. Deprettere E. F. Leupers R. Takala J. MPEG reconfigurable video coding Handbook of Signal Processing Systems 2010 Springer 43 67 – reference: Bhatt T. M. McCain D. Matlab as a development environment for FPGA design Proceedings of the 42nd annual Design Automation Conference (DAC '05) 2005 New York, NY, USA ACM – reference: Synopsys: Synphony C compiler In ESL design and verification: a prescription for electronic system-level methodology, http://www.synopsys.com/systems/blockDesign/HLS/pages/SynphonyC-Compiler.aspx – reference: Eker J. Janneck J. CAL language report ERL Technical Memo 2003 UCB/ERL M03/48 University of California at Berkeley – reference: Megalingam R. K. Venkat K. B. Vineeth S. V. Mithun M. Srikumar R. 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Snippet	In this paper, we introduce the Reconfigurable Video Coding (RVC) standard based on the idea that video processing algorithms can be defined as a library of...
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SubjectTerms	Algorithms Automation Behavior Coding Computer programs Computer Science Engineering Sciences FIFO Hardware MPEG encoders Signal and Image Processing Studies Transformations Video compression
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Title	Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs
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