Computer principles and design in Verilog HDL
Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills * Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Descri...
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| Main Authors: | , |
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| Format: | eBook Book |
| Language: | English |
| Published: |
New York
Wiley
2015
John Wiley & Sons, Incorporated Wiley-Blackwell |
| Edition: | 1 |
| Subjects: | |
| ISBN: | 1118841093, 9781118841099, 1118841123, 9781118841129 |
| Online Access: | Get full text |
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Table of Contents:
- 10.3 Data Dependency and Pipeline Stalls -- 10.3.1 Internal Forwarding -- 10.3.2 Pipeline Stall Caused by lwc1 and swc1 Instructions -- 10.3.3 Pipeline Stall Caused by Division and Square Root -- 10.4 Pipelined CPU/FPU Design in Verilog HDL -- 10.4.1 Circuit of Pipelined CPU/FPU -- 10.4.2 Circuit of the Floating-Point Unit -- 10.4.3 Circuit of the Integer Unit -- 10.4.4 Verilog HDL Codes of the Pipelined CPU/FPU -- 10.5 Memory Modules and Pipelined CPU/FPU Test -- 10.5.1 Instruction Memory and Data Memory -- 10.5.2 Test Program of Pipelined CPU/FPU -- 10.5.3 Test Waveforms of Pipelined CPU/FPU -- Exercises -- Chapter 11 Memory Hierarchy and Virtual Memory Management -- 11.1 Memory -- 11.1.1 Static Random Access Memory -- 11.1.2 Dynamic Random Access Memory -- 11.1.3 Read-Only Memory -- 11.1.4 Content Addressable Memory -- 11.1.5 Asynchronous Memory and Synchronous Memory -- 11.1.6 Memory Hierarchy -- 11.2 Cache Memory -- 11.2.1 Mapping Methods of Caches -- 11.2.2 Cache Block Replacement Algorithms -- 11.2.3 Cache Write Policies -- 11.2.4 Data Cache Design in Verilog HDL -- 11.3 Virtual Memory Management and TLB Design -- 11.3.1 Relationship of Main Memory and Virtual Memory -- 11.3.2 Segmentation Management -- 11.3.3 Paging Management -- 11.3.4 Translation Lookaside Buffer Design -- 11.3.5 Accessing Cache and TLB in Parallel -- 11.4 Mechanism of TLB-Based MIPS Memory Management -- 11.4.1 MIPS Virtual Memory Space -- 11.4.2 Organization of MIPS TLB -- 11.4.3 TLB Manipulation by Software -- Exercises -- Chapter 12 Design of Pipelined CPU with Caches and TLBs in Verilog HDL -- 12.1 Overall Structure of Caches and TLBs -- 12.2 Design of Circuits Related to Caches -- 12.2.1 Instruction Cache and Its Verilog HDL Codes -- 12.2.2 Memory Interface to Instruction and Data Caches -- 12.2.3 Pipeline Halt Circuit for Cache Misses
- 5.4.2 Verilog HDL Codes of the Control Unit -- 5.5 Test Program and Simulation Waveform -- Exercises -- Chapter 6 Exceptions and Interrupts Handling and Design in Verilog HDL -- 6.1 Exceptions and Interrupts -- 6.1.1 Types of Exceptions and Interrupts -- 6.1.2 Polled Interrupt and Vectored Interrupt -- 6.1.3 Return from Exception/Interrupt -- 6.1.4 Interrupt Mask and Interrupt Nesting -- 6.1.5 Interrupt Priority -- 6.2 Design of CPU with Exception and Interrupt Mechanism -- 6.2.1 Exception/Interrupt Handling and Related Registers -- 6.2.2 Instructions Related to Exceptions and Interrupts -- 6.2.3 Schematic of the CPU -- 6.2.4 The Verilog HDL Codes of the CPU -- 6.3 The CPU Exception and Interrupt Tests -- 6.3.1 Test Program and Data -- 6.3.2 Test Waveform and Explanations -- Exercises -- Chapter 7 Multiple-Cycle CPU Design in Verilog HDL -- 7.1 Dividing Instruction Execution into Several Clock Cycles -- 7.1.1 Instruction Fetch Cycle -- 7.1.2 Instruction Decode and Source Operand Read Cycle -- 7.1.3 Execution Cycle -- 7.1.4 Memory Access Cycle -- 7.1.5 Write Back Cycle -- 7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes -- 7.2.1 Multiple-Cycle CPU Structure -- 7.2.2 Multiple-Cycle CPU Verilog HDL Codes -- 7.3 Multiple-Cycle CPU Control Unit Design -- 7.3.1 State Transition Diagram of the Control Unit -- 7.3.2 Circuit Structure of the Control Unit -- 7.3.3 Next State Function -- 7.3.4 Output Function of Control Signal -- 7.3.5 Verilog HDL Codes of the Control Unit -- 7.4 Memory and Test Program -- 7.4.1 Memory Design -- 7.4.2 Test Program -- 7.4.3 Multiple-Cycle CPU Simulation Waveforms -- Exercises -- Chapter 8 Design of Pipelined CPU with Precise Interrupt in Verilog HDL -- 8.1 Pipelining -- 8.1.1 The Concept of Pipelining -- 8.1.2 The Baseline of Pipelined CPU -- 8.2 Pipeline Hazards and Solutions -- 8.2.1 Structural Hazards and Solutions
- Cover -- Title Page -- Copyright -- Brief Contents -- Contents -- List of Figures -- List of Tables -- Preface -- Chapter 1 Computer Fundamentals and Performance Evaluation -- 1.1 Overview of Computer Systems -- 1.1.1 Organization of Computer Systems -- 1.1.2 A Brief History of the Computer -- 1.1.3 Instruction Set Architecture -- 1.1.4 CISC and RISC -- 1.1.5 Definitions of Some Units -- 1.2 Basic Structure of Computers -- 1.2.1 Basic Structure of RISC CPU -- 1.2.2 Multithreading and Multicore CPUs -- 1.2.3 Memory Hierarchy and Virtual Memory Management -- 1.2.4 Input/Output Interfaces and Buses -- 1.3 Improving Computer Performance -- 1.3.1 Computer Performance Evaluation -- 1.3.2 Trace-Driven Simulation and Execution-Driven Simulation -- 1.3.3 High-Performance Computers and Interconnection Networks -- 1.4 Hardware Description Languages -- Exercises -- Chapter 2 A Brief Introduction to Logic Circuits and Verilog HDL -- 2.1 Logic Gates -- 2.2 Logic Circuit Design in Verilog HDL -- 2.3 CMOS Logic Gates -- 2.3.1 CMOS Inverter -- 2.3.2 CMOS NAND and NOR Gates -- 2.4 Four Levels/Styles of Verilog HDL -- 2.4.1 Transistor Switch Level -- 2.4.2 Logic Gate Level -- 2.4.3 Dataflow Style -- 2.4.4 Behavioral Style -- 2.5 Combinational Circuit Design -- 2.5.1 Multiplexer -- 2.5.2 Decoder -- 2.5.3 Encoder -- 2.5.4 Demultiplexer -- 2.5.5 Barrel Shifter -- 2.6 Sequential Circuit Design -- 2.6.1 D Latch and D Flip-Flop -- 2.6.2 JK Latch and JK Flip-Flop -- 2.6.3 T Latch and T Flip-Flop -- 2.6.4 Shift Register -- 2.6.5 FIFO Buffer -- 2.6.6 Finite State Machine and Counter Design -- Exercises -- Chapter 3 Computer Arithmetic Algorithms and Implementations -- 3.1 Binary Integers -- 3.1.1 Binary and Hexadecimal Representations -- 3.1.2 Unsigned Binary Integers -- 3.1.3 Signed Binary Integers (2's Complement Notation) -- 3.2 Binary Addition and Subtraction
- 12.3 Design of Circuits Related to TLB
- 3.2.1 Ripple Adder and Subtracter Design -- 3.2.2 Carry-Lookahead Adder Design -- 3.3 Binary Multiplication Algorithms -- 3.3.1 Unsigned Multiplier Design -- 3.3.2 Signed Multiplier Design -- 3.3.3 Wallace Tree -- 3.4 Binary Division Algorithms -- 3.4.1 Restoring Division Algorithm -- 3.4.2 Nonrestoring Division Algorithm -- 3.4.3 Goldschmidt Division Algorithm -- 3.4.4 Newton-Raphson Division Algorithm -- 3.5 Binary Square Root Algorithms -- 3.5.1 Restoring Square Root Algorithm -- 3.5.2 Nonrestoring Square Root Algorithm -- 3.5.3 Goldschmidt Square Root Algorithm -- 3.5.4 Newton-Raphson Square Root Algorithm -- Exercises -- Chapter 4 Instruction Set Architecture and ALU Design -- 4.1 Instruction Set Architecture -- 4.1.1 Operand Types -- 4.1.2 Little Endian and Big Endian -- 4.1.3 Instruction Types -- 4.1.4 Instruction Architecture -- 4.1.5 Addressing Modes -- 4.2 MIPS Instruction Format and Registers -- 4.2.1 MIPS Instruction Format -- 4.2.2 MIPS General-Purpose Registers -- 4.3 MIPS Instructions and AsmSim Tool -- 4.3.1 Some Typical MIPS Instructions -- 4.3.2 Supporting Subroutine Call and Pointer -- 4.3.3 AsmSim-A MIPS Assembler and Simulator -- 4.4 ALU Design -- Exercises -- Chapter 5 Single-Cycle CPU Design in Verilog HDL -- 5.1 The Circuits Required for Executing an Instruction -- 5.1.1 The Circuits Required by Instruction Fetch -- 5.1.2 The Circuits Required by Instruction Execution -- 5.2 Register File Design -- 5.2.1 Register File Schematic Circuit -- 5.2.2 Register File Design in Dataflow-Style Verilog HDL -- 5.2.3 Register File Design in Behavioral-Style Verilog HDL -- 5.3 Single-Cycle CPU Datapath Design -- 5.3.1 Using Multiplexers -- 5.3.2 Single-Cycle CPU Schematic Circuit -- 5.3.3 Single-Cycle CPU Verilog HDL Codes -- 5.4 Single-Cycle CPU Control Unit Design -- 5.4.1 Logic Design of the Control Unit
- 8.2.2 Data Hazards and Internal Forwarding -- 8.2.3 Control Hazards and Delayed Branch -- 8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes -- 8.3.1 The Circuit of the Pipelined CPU -- 8.3.2 Verilog HDL Codes of the Pipelined CPU -- 8.3.3 Test Program and Simulation Waveforms -- 8.4 Precise Interrupts/Exceptions in Pipelined CPU -- 8.4.1 Exception and Interrupt Types and Related Registers -- 8.4.2 Dealing with Exceptions in Pipelined CPU -- 8.5 Design of Pipelined CPU with Precise Interrupt/Exception -- 8.5.1 The Structure of the Pipelined CPU -- 8.5.2 The Verilog HDL Codes of the Pipelined CPU -- 8.5.3 Test Program for Exception and Interrupt -- 8.5.4 Simulation Waveforms of Exception and Interrupt -- Exercises -- Chapter 9 Floating-Point Algorithms and FPU Design in Verilog HDL -- 9.1 IEEE 754 Floating-Point Data Formats -- 9.2 Converting between Floating-Point Number and Integer -- 9.2.1 Converting Floating-Point Number to Integer -- 9.2.2 Converting an Integer to a Floating-Point Number -- 9.3 Floating-Point Adder (FADD) Design -- 9.3.1 Floating-Point Addition Algorithm -- 9.3.2 Circuit and Verilog HDL Codes of FADD -- 9.3.3 Pipelined FADD Design -- 9.4 Floating-Point Multiplier (FMUL) Design -- 9.4.1 Floating-Point Multiplication Algorithm -- 9.4.2 Circuit and Verilog HDL Codes of FMUL -- 9.4.3 Pipelined Wallace Tree FMUL Design -- 9.5 Floating-Point Divider (FDIV) Design -- 9.5.1 Floating-Point Division Algorithm -- 9.5.2 Circuit and Verilog HDL Codes of FDIV -- 9.6 Floating-Point Square Root (FSQRT) Design -- 9.6.1 Floating-Point Square Root Algorithm -- 9.6.2 Circuit and Verilog HDL Codes of FSQRT -- Exercises -- Chapter 10 Design of Pipelined CPU with FPU in Verilog HDL -- 10.1 CPU/FPU Pipeline Model -- 10.1.1 FPU Instructions -- 10.1.2 Basic Model of CPU/FPU Pipeline -- 10.2 Design of Register File with Two Write Ports