Complexity-effective superscalar processors

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for...

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Veröffentlicht in:Conference Proceedings. The 24th Annual International Symposium on Computer Architecture S. 206 - 218
Hauptverfasser: Palacharla, Subbarao, Jouppi, Norman P., Smith, J. E.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 01.01.1997
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Clocks
Computer systems organization > Architectures > Other architectures
Computer systems organization > Dependable and fault-tolerant systems and networks
Degradation
General and reference > Cross-computing tools and techniques > Performance
Hardware
Laboratories
Logic
Magnetic heads
Microarchitecture
Networks > Network performance evaluation
Permission
Pipelines
Registers
Theory of computation > Models of computation > Concurrency
Theory of computation > Models of computation > Concurrency > Parallel computing models
ISBN:9780897919012, 0897919017
ISSN:1063-6897
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Beschreibung
Zusammenfassung:The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of 0.8µm, 0.35µm, and 0.18µm. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future.A microarchitecture that simplifies wakeup and selection logic is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is measured in clock cycles. Furthermore, because only instructions at queue heads need to be awakened and selected, issue logic is simplified and the clock cycle is faster --- consequently overall performance is improved. By grouping dependent instructions together, the proposed microarchitecture will help minimize performance degradation due to slow bypasses in future wide-issue machines.
ISBN:9780897919012
0897919017
ISSN:1063-6897
DOI:10.1145/264107.264201