Complexity-effective superscalar processors

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for...

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Vydáno v:	Conference Proceedings. The 24th Annual International Symposium on Computer Architecture s. 206 - 218
Hlavní autoři:	Palacharla, Subbarao, Jouppi, Norman P., Smith, J. E.
Médium:	Konferenční příspěvek
Jazyk:	angličtina
Vydáno:	New York, NY, USA ACM 01.01.1997 IEEE
Edice:	ACM Conferences
Témata:	Clocks Computer systems organization > Architectures > Other architectures Computer systems organization > Dependable and fault-tolerant systems and networks Degradation General and reference > Cross-computing tools and techniques > Performance Hardware Laboratories Logic Magnetic heads Microarchitecture Networks > Network performance evaluation Permission Pipelines Registers Theory of computation > Models of computation > Concurrency Theory of computation > Models of computation > Concurrency > Parallel computing models
ISBN:	9780897919012, 0897919017
ISSN:	1063-6897
On-line přístup:	Získat plný text
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