Complexity-effective superscalar processors

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for...

Full description

Saved in:

Bibliographic Details
Published in:	Conference Proceedings. The 24th Annual International Symposium on Computer Architecture pp. 206 - 218
Main Authors:	Palacharla, Subbarao, Jouppi, Norman P., Smith, J. E.
Format:	Conference Proceeding
Language:	English
Published:	New York, NY, USA ACM 01.01.1997 IEEE
Series:	ACM Conferences
Subjects:	Clocks Computer systems organization > Architectures > Other architectures Computer systems organization > Dependable and fault-tolerant systems and networks Degradation General and reference > Cross-computing tools and techniques > Performance Hardware Laboratories Logic Magnetic heads Microarchitecture Networks > Network performance evaluation Permission Pipelines Registers Theory of computation > Models of computation > Concurrency Theory of computation > Models of computation > Concurrency > Parallel computing models
ISBN:	9780897919012, 0897919017
ISSN:	1063-6897
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!