Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm....

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Bibliographic Details
Published in:VLSI Design Vol. 2002; no. 1; pp. 455 - 468
Main Authors: Sklavos, Nikos, Papakonstantinou, Alexandros, Theoharis, Spyros, Koufopavlou, Odysseas
Format: Journal Article
Language:English
Published: Hindawi Limiteds 2002
Subjects:
IDEA algorithm
Asynchronous VLSI implementation
Encryption decryption algorithm
Cryptography
ISSN:1065-514X, 1563-5171
Online Access:Get full text
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Summary:An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6μm CMOS technology. With a system clock of up to 8MHz and a power supply of 5V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently inWireless Encryption Protocols and high speed networks.
ISSN:1065-514X
1563-5171
DOI:10.1080/1065514021000012066