Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm....

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Bibliographic Details

Published in:	VLSI Design Vol. 2002; no. 1; pp. 455 - 468
Main Authors:	Sklavos, Nikos, Papakonstantinou, Alexandros, Theoharis, Spyros, Koufopavlou, Odysseas
Format:	Journal Article
Language:	English
Published:	Hindawi Limiteds 2002
Subjects:	IDEA algorithm Asynchronous VLSI implementation Encryption decryption algorithm Cryptography
ISSN:	1065-514X, 1563-5171
Online Access:	Get full text
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