Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques
An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm....
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| Vydáno v: | VLSI Design Ročník 2002; číslo 1; s. 455 - 468 |
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| Hlavní autoři: | , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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Hindawi Limiteds
2002
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| ISSN: | 1065-514X, 1563-5171 |
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| Abstract | An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6μm CMOS technology. With a system clock of up to 8MHz and a power supply of 5V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently inWireless Encryption Protocols and high speed networks. |
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| AbstractList | An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6 μm CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently in Wireless Encryption Protocols and high speed networks. An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6μm CMOS technology. With a system clock of up to 8MHz and a power supply of 5V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently inWireless Encryption Protocols and high speed networks. |
| Author | ALEXANDROS PAPAKONSTANTINOU NIKOS SKLAVOS ODYSSEAS KOUFOPAVLOU SPYROS THEOHARIS |
| Author_xml | – sequence: 1 givenname: Nikos surname: Sklavos fullname: Sklavos, Nikos – sequence: 2 givenname: Alexandros surname: Papakonstantinou fullname: Papakonstantinou, Alexandros – sequence: 3 givenname: Spyros surname: Theoharis fullname: Theoharis, Spyros – sequence: 4 givenname: Odysseas surname: Koufopavlou fullname: Koufopavlou, Odysseas |
| BookMark | eNqFkNtKA0EMhgdRsFWfwJt9gbXJnLa9LPUIBQUr9G6ZzqZ0SjtTZ7aUfXtHqheKYC6SPyFf4E-fnfrgibFrhBuEIQwQtFIogSPkQA5an7AeKi1KhRWeZp03spbzc9ZPaZ2XJKLqsfk0HMpdOFAsnra7DW3Jt6Z1wRdhWRhf3Hkbu93nYHBL37J47VJL2-Lg2lUxTp23qxh82KdiRnbl3fue0iU7W5pNoquvesHe7u9mk8dy-vzwNBlPSyM0tuWoqRRYEA02BAtlJdgFARriuoJqITmNFqAMgGyGlajk0BpNFRlEQVUzEuKCieNdG0NKkZb1LrqtiV2NUH8-p_7jOZka_aKsO_puo3Gbf9jpkTUuutbV67CPPlusXzigQs45gK5z4shzQZ2xjCP-bKRStdRD8QFxDX-s |
| CitedBy_id | crossref_primary_10_1007_s41870_018_0123_2 |
| ContentType | Journal Article |
| DBID | 188 AAYXX CITATION |
| DOI | 10.1080/1065514021000012066 |
| DatabaseName | Chinese Electronic Periodical Services (CEPS) CrossRef |
| DatabaseTitle | CrossRef |
| DatabaseTitleList | CrossRef |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 1563-5171 |
| EndPage | 468 |
| ExternalDocumentID | 10_1080_1065514021000012066 P20151222006_200212_201612010011_201612010011_455_468 |
| GroupedDBID | .4S .DC 123 188 24P 29R 2UF 2WC 4.4 5VS AAJEY AINHJ ALMA_UNASSIGNED_HOLDINGS ARCSS CAG CAHYU CNMHZ COF CS3 E3Z EBS EDO EJD GROUPED_DOAJ H13 I-F IAO ICD IFM IL9 IPNFZ KQ8 MK~ M~E OK1 P2P RHU RHX RIG RNS TUS UGNYK 0R~ 8FE 8FG 8R4 8R5 AAMMB AAOTM AAYXX ABUWG ACCMX AEFGJ AFFHD AFKRA AGXDD AIDQK AIDYY ALUQN ARAPS AZQEC BENPR BGLVJ BPHCQ CCPQU CITATION CWDGH DWQXO GNUQQ HCIFZ ITC IVC K6V K7- OVT P62 PHGZM PHGZT PIMPY PQGLB PQQKQ PROAC Q2X |
| ID | FETCH-LOGICAL-a361t-9d750c03d1de0b5c40cbe01ae26707b42e9b05a004d873748ca6e7ea113e7d933 |
| ISICitedReferencesCount | 3 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000179649600006&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1065-514X |
| IngestDate | Sat Nov 29 01:47:34 EST 2025 Tue Nov 18 22:36:14 EST 2025 Tue Oct 01 22:51:32 EDT 2024 |
| IsDoiOpenAccess | false |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 1 |
| Keywords | IDEA algorithm Asynchronous VLSI implementation Encryption decryption algorithm Cryptography |
| Language | English |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-a361t-9d750c03d1de0b5c40cbe01ae26707b42e9b05a004d873748ca6e7ea113e7d933 |
| OpenAccessLink | https://downloads.hindawi.com/archive/2002/732414.pdf |
| PageCount | 14 |
| ParticipantIDs | crossref_primary_10_1080_1065514021000012066 crossref_citationtrail_10_1080_1065514021000012066 airiti_journals_P20151222006_200212_201612010011_201612010011_455_468 |
| PublicationCentury | 2000 |
| PublicationDate | 2002-00-00 |
| PublicationDateYYYYMMDD | 2002-01-01 |
| PublicationDate_xml | – year: 2002 text: 2002-00-00 |
| PublicationDecade | 2000 |
| PublicationTitle | VLSI Design |
| PublicationYear | 2002 |
| Publisher | Hindawi Limiteds |
| Publisher_xml | – name: Hindawi Limiteds |
| SSID | ssj0014115 |
| Score | 1.5443287 |
| Snippet | An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous... |
| SourceID | crossref airiti |
| SourceType | Enrichment Source Index Database Publisher |
| StartPage | 455 |
| Title | Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques |
| URI | https://www.airitilibrary.com/Article/Detail/P20151222006-200212-201612010011-201612010011-455-468 |
| Volume | 2002 |
| WOSCitedRecordID | wos000179649600006&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVWIB databaseName: Wiley Online Library Open Access customDbUrl: eissn: 1563-5171 dateEnd: 20181231 omitProxy: false ssIdentifier: ssj0014115 issn: 1065-514X databaseCode: 24P dateStart: 19930101 isFulltext: true titleUrlDefault: https://authorservices.wiley.com/open-science/open-access/browse-journals.html providerName: Wiley-Blackwell |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV3NjtMwELbKwgEOiF9RWJAP3CDaJHbi5LhaikBUpVLLqnCJHMfVVluSqOmWLad9BB5tn4EnYfyTNGWrFXvg0jZpYquZz_Y30_E3CL1OCUAlnfpO6AoBDorHnVjKCAYeC4CdxyzWNZaO-2wwiCaTeNjpXNZ7YVZzlufR-Xlc_ldTwzkwtto6ewNzN43CCfgMRodXMDu8_pPh-8WPJoOhVDXQjALwd7vJSNNDGNS9XCzWer6Art7J-sBKmJv47GG1zoVSz1V5suNa7bVqE9rj_ujjm0yngSiy-hUely0PMoImfpq9xK1ww-h0zlcmtW8wOy0aRj-ERdty1eUM-mttvllsrlJKAieqbKLuoFy3vvpUnE2Lkq_m5t7P2bpS8c-tqEYrxAk-auAAjZuYFcpOyyGBc6ZYSzNvB1fwaSZhaoR_7XpOTdmeK0uFya1UvUFnyvPVQTk33CHM_deC2aQxelZfdUcjt9Btn4GzprTG6bD5X4t6uqZG8xtrHazIPdjRCLAiPlPaVi3S1GI_4wfovnVb8KGB20PUkfkjdK8lZvkYfQPg_b74pSGHtyGHiynmOd5A7mADOGwAhxXgcBtweAO4J-jL-9746INjK3c4nITe0okzIKLCJZmXSTcNBHVFKmEekH7IXJZSX8apG3AYtVnElACS4KFkknsekSyLCXmK9vIil88QJlRJOMbg11NGUwYMlkRkKgLC0jDKuOyinnlGiR2DVTIEUgs81lfRskQnIfnwBq6NyvyA9Wz7ANCSAEa6yK8fcSKsPL6q0jJPrrFyF71tbiqNOsx1lz-_2eUv0F1de0gH_PbR3nJxJl-iO2K1nFWLVxpYfwD4L6gv |
| linkProvider | Wiley-Blackwell |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Low%E2%80%90power+Implementation+of+an+Encryption%2FDecryption+System+with+Asynchronous+Techniques&rft.jtitle=VLSI+design+%28Yverdon%2C+Switzerland%29&rft.au=Sklavos%2C+Nikos&rft.au=Papakonstantinou%2C+Alexandros&rft.au=Theoharis%2C+Spyros&rft.au=Koufopavlou%2C+Odysseas&rft.date=2002&rft.issn=1065-514X&rft.eissn=1563-5171&rft.volume=15&rft.issue=1&rft.spage=455&rft.epage=468&rft_id=info:doi/10.1080%2F1065514021000012066&rft.externalDBID=n%2Fa&rft.externalDocID=10_1080_1065514021000012066 |
| thumbnail_m | http://cvtisr.summon.serialssolutions.com/2.0.0/image/custom?url=https%3A%2F%2Fwww.airitilibrary.com%2Fjnltitledo%2FP20151222006-c.jpg |